CHAPTER 4 PORT FUNCTIONS
Figure 4-6. Block Diagram of P33 and P35
EVDD
WRPU
PU3
P-ch
PU3n
WRPF
WRPMC
WRPM
PFC3
PFC3n
PMC3
PMC3n
PM3
PM3n
WRPORT
TO00, TO01 output
P33/TI000/TO00
P35/TI010/TO01
Output latch
(P3n)
Address
RD
TI000, TI010 input
Remarks 1. PU3: Pull-up resistor option register 3
PFC3: Port 3 function control register
PM3: Port 3 mode register
PMC3: Port 3 mode control register
RD:
WR: Port 3 write signal
2. n = 3, 5
Port 3 read signal
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