µPD178023, 178024
Figure 3-9. Block Diagram of Serial Interface (SIO3)
Internal bus
8
Serial I/O shift
registe 3 (SIO3)
SI3/P70
PM71
SO3/P71
P71 output latch
Interrupt request
signal generation
circuit
Serial clock
counter
SCK3/P72
INTCSI3
f
f
f
X
X
X
/24
/25
/26
Serial clock
control circuit
Selector
PM72
P72 output latch
Figure 3-10. Block Diagram of Serial Interface (UART0)
Internal bus
Asynchronous serial interface
mode register 0 (ASIM0)
Receive buffer
register 0
(RXB0)
TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0
0
Asynchronous serial interface
status register 0 (ASIS0)
Receive shift
register 0
(RX0)
Transmit shift
register 0
(TXS0)
PE0 FE0 OVE0
RXD0/P74
TXD0/P75
Reception
control circuit
(parity check)
INTSER0
PM75
P75 output latch
INTSR0
Transmission
control circuit
(parity append)
INTST0
Baud rate
generator
fX/2-fX
/28
Data Sheet U14126EJ1V0DS00
25
NEC [ NEC ]
