µPD178023, 178024
3.5 A/D Converter
An A/D converter with a resolution of 8 bits × 6 channels is provided.
Figure 3-7. Block Diagram of A/D Converter
ANI0/P10
Sample & hold circuit
ANI1/P11
VDD
Voltage comparator
ANI2/P12
ADCS3
ANI3/P13
ANI4/P14
ANI5/P15
Successive
GND
approximation
register (SAR)
Control
circuit
INTAD3
Control
circuit
Voltage
comparator
Power-fail comparison threshold
value register 3 (PFT3)
A/D conversion result
register 3 (ADCR3)
4
ADS33 ADS32 ADS31 ADS30
ADCS3
0
FR32 FR31 FR30
0
0
0
PFEN3 PFCM3 PFHRM3
Analog input channel
specification register 3 (ADS3)
A/D converter mode
register 3 (ADM3)
Power-fail comparison mode
register 3 (PFM3)
Internal bus
Data Sheet U14126EJ1V0DS00
23
NEC [ NEC ]
