µPD178023, 178024
Figure 3-5. Block Diagram of Watchdog Timer
INTWDT
RESET
Clock input
control circuit
Divided clock
Divider circuit
f
/28
X
select circuit
Output
control
circuit
RUN
Division mode
select circuit
3
WDT mode signal
OSTS2OSTS1OSTS0
Oscillation stabilization Watchdog timer clock
WDCS2 WDCS1 WDCS0
RUN WDTM4 WDTM3
Watchdog timer mode
register (WDTM)
time select register (OSTS) select register (WDCS)
Internal bus
3.4 Buzzer Output Control Circuit
The buzzer output frequency is selected as follows.
• BEEP0 ... 1 kHz/1.5 kHz/3 kHz/4 kHz
Figure 3-6. Block Diagram of Buzzer Output Control Circuit (BEEP0)
1 kHz
1.5 kHz
Selector
BEEP0/P36
3 kHz
4 kHz
Output latch
PM36
(P36)
BEEP BEEP BEEP BEEP0 clock select
CL02 CL01 CL00 register (BEEPCL0)
Internal bus
22
Data Sheet U14126EJ1V0DS00
NEC [ NEC ]
