µPD178023, 178024
3.2 Clock Generation Circuit
The instruction execution time can be changed as follows:
• 0.45 µs/0.89 µs/1.78 µs/3.56 µs/7.11 µs (system clock: 4.5-MHz crystal resonator)Note
Figure 3-1. Block Diagram of Clock Generation Circuit
Prescaler
X1
X2
Clock to other than
peripheral hardware
System
clock
oscillator
Prescaler
f
X
f
X
24
f
X
23
Standby
control
circuit
Wait
control
circuit
f
X
22
CPU clock
f
X
(fCPU
)
2
3
STOP
0
0
0
0
0
PCC0
PCC1
PCC2
Processor clock control register (PCC)
Internal bus
3.3 Timers
Four timer channels are provided.
• Basic timer
• 8-bit timer/event counter : 2 channels
• Watchdog timer : 1 channel
: 1 channel
Figure 3-2. Block Diagram of Basic Timer
Divider circuit
4.5 MHz
INTBTM0
20
Data Sheet U14126EJ1V0DS00
NEC [ NEC ]
