CHAPTER 4 PORT FUNCTIONS
4.2.5 Port 5
This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in
1-bit units by using port mode register 5 (PM5). For a mask ROM version, use of an on-chip pull-up resistor can be
specified by a mask option.
This port is set in the input mode when the RESET signal is input.
Figure 4-13 shows a block diagram of port 5.
Figure 4-13. Block Diagram of P50 to P53
VDD
RD
Mask option resistor
Mask ROM version only.
For flash memory version,
a pull-up resistor is not
incorporated.
P50 to P53
WRPORT
Output latch
(P50 to P53)
N-ch
WRPM
PM50 to PM53
PM: Port mode register
RD: Port 5 read signal
WR: Port 5 write signal
User’s Manual U15075EJ1V0UM00
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NEC [ NEC ]
