CHAPTER 3 CPU ARCHITECTURE
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed
RAM area can be set as the stack area.
Figure 3-15. Stack Pointer Configuration
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)
from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-16 and 3-17.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 3-16. Data to Be Saved to Stack Memory
Interrupt
PUSH rp
instruction
CALL, CALLT
instructions
_
_
_
_
SP SP
SP
3
3
2
1
_
_
_
_
_
_
SP SP
SP
2
2
1
SP SP
SP
2
2
1
PC7 to PC0
PC15 to PC8
PSW
Lower
register pairs
SP
PC7 to PC0
Higher
register pairs
SP
SP
PC15 to PC8
SP
SP
SP
SP
Figure 3-17. Data to Be Restored from Stack Memory
POP rp
RET instruction
RETI instruction
instruction
Lower
register pairs
SP
SP
SP + 1
PC7 to PC0
SP
PC7 to PC0
PC15 to PC8
PSW
Higher
register pairs
PC15 to PC8
SP + 1
SP + 1
SP + 2
SP SP + 2
SP SP + 2
SP SP + 3
User’s Manual U15075EJ1V0UM00
63
NEC [ NEC ]
