CHAPTER 16 RESET FUNCTION
The following two operations are available to generate reset signals.
(1) External reset input by RESET pin
(2) Internal reset by watchdog timer runaway time detection
External and internal reset have no functional differences. In both cases, program execution starts at the address
at 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each
hardware is set to the status shown in Table 16-1. Each pin has a high impedance during reset input or during
oscillation stabilization time just after reset clear.
When a high level is input to the RESET pin, the reset is cleared and program execution is started after the
oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared
after reset, and program execution is started after the oscillation stabilization time has elapsed (see Figures 16-2 to
16-4.)
Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.
2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset
input. However, the port pins become high impedance.
Figure 16-1. Block Diagram of Reset Function
RESET
Reset signal
Reset controller
Over-
flow
Interrupt function
Count clock
Watchdog timer
Stop
User’s Manual U15075EJ1V0UM00
287
NEC [ NEC ]
