CHAPTER 6 16-BIT TIMER
(2) Buzzer output control register 90 (BZC90)
This register selects a buzzer frequency based on fcl selected with the count clock select bits (TCL901 and
TCL900), and controls the output of the square wave.
BZC90 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets BZC90 to 00H.
Figure 6-3. Format of Buzzer Output Control Register 90
Address After reset R/W
R/WNote
Symbol
BZC90
7
0
6
0
5
0
4
0
3
<0>
2
1
BCS902 BCS901 BCS900 BZOE90
FF49H
00H
Buzzer frequency
BCS902 BCS901 BCS900
fcl = f
X
/22
fcl = f
X
/26
fcl = f
X
/27
fcl = fXT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fcl/24 (78.1 kHz)
fcl/25 (39.1 kHz)
fcl/28 (4.88 kHz)
fcl/29 (2.44 kHz)
fcl/210 (1.22 kHz)
fcl/211 (610 Hz)
fcl/212 (305 Hz)
fcl/213 (153 Hz)
fcl/24 (4.88 kHz)
fcl/25 (2.44 kHz)
fcl/28 (305 Hz)
fcl/29 (153 Hz)
fcl/210 (76 Hz)
fcl/211 (38 Hz)
fcl/212 (19 Hz)
fcl/213 (10 Hz)
fcl/24 (2.44 kHz)
fcl/25 (1.22 kHz)
fcl/28 (153 Hz)
fcl/29 (76 Hz)
fcl/210 (38 Hz)
fcl/211 (19 Hz)
fcl/212 (10 Hz)
fcl/213 (5 Hz)
fcl/24 (2.05 kHz)
fcl/25 (1.02 kHz)
fcl/28 (128 Hz)
fcl/29 (64 Hz)
fcl/210 (32 Hz)
fcl/211 (16 Hz)
fcl/212 (8 Hz)
fcl/213 (4 Hz)
BZOE90
0
Buzzer port output control
Disables buzzer port output.
Enables buzzer port output.
1
Note Bits 4 to 7 must be set to 0.
Caution If the subclock is selected as the count clock (TCL901 = 1, TCL900 = 1: see Figure 6-2
Format of 16-Bit Timer Mode Control Register 90), the subclock is not synchronized when
buzzer port output is enabled. In this case, the capture function and TM90 read function
are disabled. In addition, the count value of TM90 is undefined.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
User’s Manual U15075EJ1V0UM00
121
NEC [ NEC ]
