NTC Proprietary
Level: Property
DDR3(L)-2Gb SDRAM
NT5CB(C)256M8JQ/NT5CB(C)128M16JR
Pulled-in Refresh Commands (Example)
tREFI
9 tREFI
t
tRFC
8 REF-Commands pulled-in
Self-Refresh Operation
The Self-Refresh command can be used to retain data in the DDR3(L) SDRAM, even if the rest of the system is powered
down. When in the Self-Refresh mode, the DDR3(L) SDRAM retains data without external clocking. The DDR3(L) SDRAM
device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Entry (SRE) Command is defined by
having , RA, A, and E held low with WE high at the rising edge of the clock.
Before issuing the Self-Refreshing-Entry command, the DDR3(L) SDRAM must be idle with all bank precharge state with
tRP satisfied. Also, on-die termination must be turned off before issuing Self-Refresh-Entry command, by either registering
ODT pin low “ODTL + 0.5tCK” prior to the Self-Refresh Entry command or using MRS to MR1 command. Once the Self-
Refresh Entry command is registered, CKE must be held low to keep the device in Self-Refresh mode. During normal
operation (DLL on), MR1 (A0=0), the DLL is automatically disabled upon entering Self-Refresh and is automatically enabled
(including a DLL-RESET) upon exiting Self-Refresh.
When the DDR3(L) SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE and REET, are
“don’t care”. For proper Self-Refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VRefCA,
and VRefDQ) must be at valid levels. The DRAM initiates a minimum of one Refresh command internally within tCKE period
once it enters Self-Refresh mode.
The clock is interna during Self-Refresh operation to save power. The minimum time that the DDR3(L) SDRAM must remain
in Self-Refresh mode is tCKESR. The user may change the external clock frequency or halt the external clock tCKSRE after
Self-Refresh entry is registered; however, the clock must be restarted and stable tCKSRX before the device can exit Self-
Refresh mode.
The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE going
back HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or Deselect on
command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL
can be issued to the device to allow for any internal refresh in progress. Before a command which requires a locked DLL
can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements must be satisfied.
Version 1.4
05/2019
59
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