NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
NanoAmp Solutions, Inc.
Block Diagram (32Mb x 8)
CKE
CK
CK
CS
WE
CAS
RAS
Bank3
Bank2
Bank1
CK, CK
DLL
Mode
13
Registers
8192
Bank0
Memory
Array
Data
13
15
(8192 x 512 x 16)
8
8
8
16
Sense Amplifiers
1
DQS
Generator
DQ0-DQ7,
DM
COL0
Mask
DQS
Input
Register
1
I/O Gating
DM Mask Logic
16
2
DQS
1
1
A0-A12,
BA0, BA1
Write
15
1
FIFO
1
&
16
2
16
2
512
Drivers
(x16)
8
8
8
8
8
clk
clk
Column
Decoder
in
out
Data
9
COL0
CK,
CK
Column-Address
Counter/Latch
10
COL0
1
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
6
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
NANOAMP [ NANOAMP SOLUTIONS, INC. ]
