N64T1618CBB
Advance Information
NanoAmp Solutions, Inc.
BUS OPERATING MODES
FUNCTIONAL DESCRIPTION
The N64T1618CBB product incorporates the burst
mode interface found on Flash products targeting
low-power wireless applications. This bus interface
supports asynchronous, page-mode and burst-
mode READ and WRITE transfers. The specific
interface supported is defined by the value loaded
into the Bus Configuration Register. Page Mode is
controlled by the Refresh Configuration Register
(RCR[7]).
In general, the N64T1618CBB device can be con-
sidered a high-density alternative to SRAM prod-
ucts popular in low-power portable applications.
The N64T1618CBB contains 67,108,864 bits orga-
nized as 4,194,304 addresses x 16 bits. The
device implements the same high-speed bus inter-
face found on burst-mode Flash products.
The bus interface supports both asynchronous and
burst-mode transfers. Page-mode accesses are
also included as a bandwidth-enhancing extension
to the asynchronous read protocol.
Asynchronous Mode
The N64T1618CBB device default power-up state
is in the asynchronous operating mode. This mode
uses the standard SRAM control bus (CE#, OE#,
WE#, LB#/UB#). READ operations (Figure 3) are
initiated by bringing CE#, OE# and LB#/UB# LOW
while keeping WE# HIGH. Valid data will be driven
out of the I/O pins after the specified access time
has elapsed. WRITE operations (Figure 4) occur
when CE#, WE# and LB#/UB# are driven LOW.
During asynchronous write operations the OE#
level is a “don't care,” and WE# will override OE#.
The data to be written will be latched on the rising
edge of CE#, WE# or LB#/UB# (whichever occurs
first). Asynchronous operations (page-mode dis-
abled) can either use the ADV input to latch the
address, or ADV can be driven LOW during the
entire READ/WRITE operation.
POWER-UP INITIALIZATION
The N64T1618CBB includes an on-chip voltage
sensor used to launch the power-up initialization
process. Initialization will configure the Bus Config-
uration Register (BCR) and the Refresh Configura-
tion Register (RCR) with their default settings (See
Tables 3 and 6). VCC and VCCQ must be applied
simultaneously. Once they reach a stable level
above 1.70V, the device will require 150µs to com-
plete its self-initialization process. During the initial-
ization period the CE# pin should remain HIGH.
Once initialization has completed, the device is
ready for normal operation.
Figure 2. Power-Up Initialization
Timing
The WAIT pin will be driven while the device is
enabled and its state should be ignored.
Vcc=1.70V
tPU>150µs
Device ready for
normal operation
VCC
VccQ
Device Initialization
Stock No. 23310-H 1/05
This is an ADVANCE DATASHEET and subject to change without notice.
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NANOAMP [ NANOAMP SOLUTIONS, INC. ]
