N64T1618CBB
Advance Information
NanoAmp Solutions, Inc.
tain data integrity as temperatures increase. More
frequent refresh is required due to increased leak-
age of the DRAM capacitive storage elements as
temperatures rise. A decreased refresh rate at
lower temperatures will facilitate a savings in
standby current. TCR allows for refresh at four dif-
ferent temperature thresholds (15°C, 45°C, 70°C
and 85°C). The setting selected must be for a tem-
perature higher than the case temperature of the
device. If the case temperature were 50°C the sys-
tem could minimize self-refresh current consump-
tion by selecting the 70°C setting. The 15°C and
45°C settings would result in inadequate refreshing
and cause data corruption.
LOW-POWER OPERATION
Standby Mode Operation
During standby the device current consumption is
reduced to the level necessary to perform the
DRAM refresh operation. Standby operation occurs
when the CE# pin is HIGH and there are no trans-
actions in progress. The device will enter standby
operation on completion of a READ or WRITE
operation, or when the address and control inputs
remain static for an extended period of time. This
“active” standby mode will continue until a change
occurs to the address or control inputs.
Deep Power Down Operation
CONFIGURATION REGISTERS
Deep Power Down (DPD) operation disables all
refresh-related activity. This mode would be used if
the system does not require the storage provided
by the device. Any stored data will become cor-
rupted once the DPD is enabled. Once refresh
activity has been re-enabled, the device will require
150µs to perform an initialization procedure before
normal operations can resume. During this 150µs
period, the current consumption will be higher than
the specified standby levels, but considerably
lower than the active-current specification.
Two WRITE-only user-accessible configuration
registers have been included to define device oper-
ation. The Bus Configuration Register (BCR)
defines how the N64T1618CBB interacts with the
system memory bus and is nearly identical to its
counterpart found on burst-mode Flash devices.
The Refresh Configuration Register (RCR) is used
to control how refresh is performed on the DRAM
array. These registers are automatically loaded
with default settings during power-up and can be
updated any time the devices are operating in a
standby state.
Partial Array Self Refresh
Configuration Registers
Partial Array Self Refresh (PASR) restricts refresh
operation to a portion of the total memory array.
This feature allows the device to reduce standby
current by refreshing only that part of the memory
array required by the host system. The refresh
options are full array, ¾ array, ½ array, ¼ array or
none of the array. The mapping of these partitions
can start at either the beginning or the end of the
address map (See Table 7). READ and WRITE
operations to address ranges receiving refresh will
not be affected. Data stored in addresses not
receiving refresh will become corrupted.
The Configuration Registers (BCR and RCR)
define how the device interacts with the system
memory bus. Page mode operation is enabled by a
bit contained in the Refresh Configuration Register.
The registers are loaded using either a synchro-
nous or an asynchronous WRITE operation when
the Control Register Enable pin (CRE) is HIGH
(see Figure 11 and Figure 12). When CRE is LOW,
a normal WRITE operation will access the memory
array. The values placed on address pins [A21:A0]
are latched into the BCR or RCR on the rising edge
of ADV#, CE#, or WE#, which ever occurs first.
UB# and LB# are “don’t care.” The BCR is
accessed when A19 is HIGH and the RCR is
accessed when A19 is LOW.
Temperature-Compensated Refresh
Temperature Compensated Refresh (TCR) is used
to adjust the refresh rate depending on the device
operating temperature. DRAM technology requires
increasingly frequent refresh operations to main-
MEG
Stock No. 23310-H 1/05
This is an ADVANCE DATASHEET and subject to change without notice.
11
NANOAMP [ NANOAMP SOLUTIONS, INC. ]
