欢迎访问ic37.com |
会员登录 免费注册
发布采购

N64T1618CBBZ-77IL 参数 Datasheet PDF下载

N64T1618CBBZ-77IL图片预览
型号: N64T1618CBBZ-77IL
PDF下载: 下载PDF文件 查看货源
内容描述: [DRAM]
分类和应用: 动态存储器
文件页数/大小: 50 页 / 959 K
品牌: NANOAMP [ NANOAMP SOLUTIONS, INC. ]
 浏览型号N64T1618CBBZ-77IL的Datasheet PDF文件第1页浏览型号N64T1618CBBZ-77IL的Datasheet PDF文件第2页浏览型号N64T1618CBBZ-77IL的Datasheet PDF文件第3页浏览型号N64T1618CBBZ-77IL的Datasheet PDF文件第5页浏览型号N64T1618CBBZ-77IL的Datasheet PDF文件第6页浏览型号N64T1618CBBZ-77IL的Datasheet PDF文件第7页浏览型号N64T1618CBBZ-77IL的Datasheet PDF文件第8页浏览型号N64T1618CBBZ-77IL的Datasheet PDF文件第9页  
N64T1618CBB  
Advance Information  
NanoAmp Solutions, Inc.  
Table 2. Functional Description  
Asynchronous Mode  
UB#/  
LB#  
WAIT5 I/O0-I/O151  
MODE  
POWER  
CLK ADV# CE#  
OE#  
WE# CRE  
NOTES  
L1  
L1  
X
X
Read  
Active  
Active  
X
X
L
L
L
L
L
H
L
L
L
Low-Z Data-Out  
Low-Z Data-In  
4
4
2
Write  
X
Standby  
No Operation Idle  
Configuration Active  
Register  
Standby  
X
X
X
X
X
L
H
L
L
X
X
H
X
X
L
L
L
H
High-Z High-Z  
Low-Z X  
Low-Z High-Z  
4, 6  
X
DPD  
Deep Power Down  
X
X
H
X
X
X
X
High-Z High-Z  
9
Burst Mode  
UB#/  
LB#  
CLK8  
WAIT5 I/O0-I/O151  
MODE  
POWER  
ADV# CE#  
OE#  
WE# CRE  
NOTES  
Async. Read Active  
Async. Write Active  
X
X
X
X
P
L
L
X
X
L
L
L
H
L
L
L
X
X
X
X
H
L
X
X
H
L
L
L
L
L
L
L
X
X
L
Low-Z Data-Out  
Low-Z Data-In  
High-Z High-Z  
Low-Z X  
1,4  
1,4  
2
4,6  
Standby  
Standby  
No Operation Idle  
Initial Burst  
Read  
Initial Burst  
Write  
Active  
Active  
Low-Z Data-Out  
1,3,4,7  
P
P
L
L
L
H
X
L
L
L
X
X
Low-Z Data-In  
3,4,7  
3,4,7  
Burst Continue Active  
H
X
Low-Z Data-In or  
Data-Out  
Burst Suspend Active  
Configuration Active  
Register  
X
P
X
L
L
L
H
H
X
L
L
H
X
X
Low-Z High-Z  
Low-Z High-Z  
3,4  
3,7  
DPD  
Deep Power Down  
X
X
H
X
X
X
X
High-Z High-Z  
9
NOTE: P symbolizes clock pulse  
1. When UB# and LB# are in select mode (LOW), I/O0-I/O15 are affected as shown. When only LB# is in select mode, I/O0-I/O7 are  
affected as shown. When only UB# is in the select mode, I/O8-I/O15 are affected as shown.  
2. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.  
3. Burst Mode operation is initialized through the Bus Configuration Register (BCR[15]).  
4. The device will consume active power in this mode whenever addresses are changed.  
5. The WAIT polarity is configured through the Bus Configuration Register (BCR[10]).  
6. VIN = VCCQ or 0V, all device pins must be static (unswitched) in order to achieve standby current.  
7. The clock polarity is configured through the Bus Configuration Register (BCR[6]).  
8. P refers to a clock pulse.  
9. DPD is maintained until the Refresh Configuration Register is reconfigured.  
2MEG refers to  
Stock No. 23310-H 1/05  
This is an ADVANCE DATASHEET and subject to change without notice.  
4