N64T1618CBB
Advance Information
NanoAmp Solutions, Inc.
mode takes advantage of the fact that adjacent
Page Mode READ Operation
addresses can be read in a shorter period of time
than random addresses. WRITE operations do not
include comparable page mode functionality. CE#
must be driven HIGH upon completion of a page-
mode access. The WAIT pin will be driven while
the device is enabled and its state should be
ignored. Page mode is enabled by setting RCR[7]
to HIGH. WRITE operations do not include compa-
rable page-mode functionality. ADV must be driven
LOW during all page-mode READ accesses.
Page mode is a performance-enhancing extension
to the standard asynchronous READ operation. In
page-mode capable products, an initial asynchro-
nous read access is performed, and then adjacent
addresses can be read quickly by simply changing
the low-order address. The lower address bits,
depending on selected page size, are used to
determine the specific word location within the
page. The upper address bits must remain fixed
during the entire page mode access. Figure 5
shows the timing for a page mode access. Page
Figure 5. PAGE READ Operation (ADV=LOW)
CE#
OE#
WE#
Add[0]
Add[1] Add[2]
Add[3]
ADDRESS
t
t
t
t
APA
AA
APA
APA
D[0]
D[1]
D[2]
D[3]
DATA
LB#,UB#
DON’T CARE
BCR defines how many clock cycles elapse before
the initial data value is transferred between the pro-
cessor and the device. The WAIT output will be
asserted as soon as a burst is initiated and will be
deasserted to indicate when data is to be trans-
ferred into (or out of) the memory. The WAIT pin
will again be asserted if the burst crosses a row
boundary. Once the device has restored the previ-
ous row's data and accessed the next row, the
WAIT pin will be deasserted and the burst can con-
tinue (See Figure 27). Rows consist of 128 words
and are defined by the address values placed on
[A21:A7].
Burst Mode
Burst-mode operations allow high-speed synchro-
nous READ and WRITE transactions. Burst opera-
tions consist of a multi-clock sequence that must
be performed in an ordered fashion. After CE#
goes LOW, the address to access is latched on the
next rising edge of CLK or ADV# (whichever
occurs first). During this first clock rising edge the
WE# pin indicates whether the operation is going
to be a READ (WE#=HIGH, Figure 6) or WRITE
(WE#=LOW, Figure 7). The size of a burst can be
specified in the BCR as either fixed length or con-
tinuous. Fixed-length bursts consist of four, eight or
sixteen words. Continuous bursts have the ability
to start at a specified address and burst through
the entire memory. The latency count stored in the
Stock No. 23310-H 1/05
This is an ADVANCE DATASHEET and subject to change without notice.
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NANOAMP [ NANOAMP SOLUTIONS, INC. ]
