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N64T1618CBBZ-73IL-TR 参数 Datasheet PDF下载

N64T1618CBBZ-73IL-TR图片预览
型号: N64T1618CBBZ-73IL-TR
PDF下载: 下载PDF文件 查看货源
内容描述: [DRAM]
分类和应用: 动态存储器
文件页数/大小: 50 页 / 959 K
品牌: NANOAMP [ NANOAMP SOLUTIONS, INC. ]
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N64T1618CBB  
Advance Information  
NanoAmp Solutions, Inc.  
cally loaded with default settings during power-up  
and can be updated any time during normal opera-  
tion. Special attention has been focused on  
standby current consumption during self-refresh.  
The N64T1618CBB device includes three system-  
accessible mechanisms used to minimize standby  
current. Partial Array Self Refresh (PASR) limits  
refresh to only that part of the DRAM array that  
contains essential data. Temperature Compen-  
sated Refresh (TCR) is used to adjust the refresh  
rate according to the ambient temperature. The  
refresh rate can be decreased at lower tempera-  
tures to minimize current consumption during  
standby. Deep Power Down (DPD) halts the  
refresh operation altogether and is used when no  
vital information is stored in the device. These  
three refresh mechanisms are adjusted through the  
Refresh Configuration Register.  
General Description  
The N64T1618CBB is a 64Mb device organized as  
4M x 16 bits. These devices include the industry  
standard burst mode Flash interface that dramati-  
cally increases read/write bandwidth when com-  
pared with other low-power SRAM or Pseudo-  
SRAM offerings. To operate seamlessly on a burst  
Flash bus, a transparent self-refresh mechanism is  
incorporated. The hidden refresh requires no addi-  
tional support from the system memory controller  
and has no significant impact on device read/write  
performance. Two user-accessible control registers  
define device operation. The Bus Configuration  
Register (BCR) defines how the device interacts  
with the system memory bus and is nearly identical  
to its counterpart found on burst-mode Flash  
devices. The Refresh Configuration Register  
(RCR) is used to control how refresh is performed  
on the DRAM array. These registers are automati-  
Figure 1. Functional Block Diagram  
A[21-0]  
Address Decode  
Logic  
Input/  
Output  
Mux  
4,096Kx 16  
Refresh Configuration  
Register  
I/O0 - I/O7  
DRAM  
MEMORY  
ARRAY  
and  
Buffers  
Bus Configuration  
Register  
I/O8 - I/O15  
CE#  
WE#  
OE#  
CLK  
Control  
Logic  
ADV#  
CRE  
WAIT  
LB#  
UB#  
Stock No. 23310-H 1/05  
This is an ADVANCE DATASHEET and subject to change without notice.  
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