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N16D1633LPAZ-70I 参数 Datasheet PDF下载

N16D1633LPAZ-70I图片预览
型号: N16D1633LPAZ-70I
PDF下载: 下载PDF文件 查看货源
内容描述: [DRAM]
分类和应用: 动态存储器
文件页数/大小: 26 页 / 582 K
品牌: NANOAMP [ NANOAMP SOLUTIONS, INC. ]
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N16D1633LPA  
Advance Information  
NanoAmp Solutions, Inc.  
Table 4: Command Truth Table  
COMMAND  
CKEn-1  
CKEn  
CS  
RAS  
CAS  
WE  
DQM  
ADDR  
A10  
Note  
Command Inhibit (NOP)  
No Operation (NOP)  
Mode Register Set  
H
H
H
H
X
X
X
X
H
L
L
L
X
H
L
X
H
L
X
H
L
X
X
X
X
X
X
OP-CODE  
OP-CODE  
4
4
Extended Mode Register Set  
L
L
L
Active (select bank and activate  
row)  
H
X
L
L
H
H
X
Bank/Row  
Read  
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
H
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
H
H
H
L
L
H
L
L
L
L
H
H
L
L
L
L/H  
L/H  
L/H  
L/H  
X
X
X
X
X
Bank/Col  
L
H
L
H
H
L
5
5
5
5
Read with Autoprecharge  
Write  
Write with Autoprecharge  
Precharge All Banks  
Precharge Selected Bank  
Burst stop  
Bank/Col  
Bank/Col  
Bank/Col  
X
L
H
H
H
L
L
L
Bank  
X
X
X
Auto Refresh  
Self Refresh Entry  
H
H
X
H
X
H
X
H
X
V
3
3
L
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
Self Refresh Exit  
L
H
L
H
L
X
X
X
X
X
X
X
X
2
Precharge Power Down Entry  
Precharge Down Exit  
Clock Suspend Entry  
H
L
H
Clock Suspend Exit  
Deep Power Down Entry  
Deep Power Down Exit  
L
H
L
H
L
H
X
X
X
X
X
X
X
X
L
H
H
L
6
Note :  
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previoys clock edge.  
H: High Level, L: Low Level, X: Don't Care, V: Valid  
2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once  
tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A mimum  
of two NOP commands must be provided during tXSR period.  
3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.  
4. A0-A10 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended  
mode register set.  
5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and  
Read DQM Latency is 2 CLK.  
6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is  
assigned to the Deep Power Down function.  
Stock No. 23395- Rev I 5/05  
12  
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.