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N02M0818L2A 参数 Datasheet PDF下载

N02M0818L2A图片预览
型号: N02M0818L2A
PDF下载: 下载PDF文件 查看货源
内容描述: 2MB超低功耗异步医疗CMOS SRAM 256Kx8位 [2Mb Ultra-Low Power Asynchronous Medical CMOS SRAM 256Kx8 bit]
分类和应用: 医疗静态存储器
文件页数/大小: 8 页 / 216 K
品牌: NANOAMP [ NANOAMP SOLUTIONS, INC. ]
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NanoAmp Solutions, Inc.  
N02M0818L2A  
1
Absolute Maximum Ratings  
Item  
Symbol  
VIN,OUT  
VCC  
Rating  
–0.3 to VCC+0.3  
–0.3 to 3.0  
500  
Unit  
V
Voltage on any pin relative to VSS  
Voltage on VCC Supply Relative to VSS  
Power Dissipation  
V
PD  
mW  
oC  
oC  
oC  
TSTG  
Storage Temperature  
–40 to 125  
TA  
Operating Temperature  
-20 to +60  
240oC, 10sec(Lead only)  
TSOLDER  
Soldering Temperature and Time  
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not  
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
1
Recommended Operating Limits (Not all inclusive values tested)  
Item  
Symbol  
VCC  
VDR  
VIH  
Test Conditions  
Min.  
1.3  
Max  
Unit  
V
Core Supply Voltage  
Data Retention Voltage  
Input High Voltage  
Input Low Voltage  
2.3  
Chip Disabled (Note 3)  
1.0  
V
0.7VCCQ VCCQ+0.5  
V
VIL  
0.3VCCQ  
–0.5  
V
VOH  
VOL  
ILI  
IOH = 0.2mA  
IOL = -0.2mA  
VCCQ–0.3  
Output High Voltage  
Output Low Voltage  
Input Leakage Current  
Output Leakage Current  
V
0.3  
0.1  
0.1  
V
VIN = 0 to VCC  
µA  
µA  
ILO  
OE = VIH or Chip Disabled  
VCC=2.3 V, VIN=VIH or VIL  
Chip Enabled, IOUT = 0  
Read/Write Operating Supply Current  
ICC1  
ICC2  
2.5  
mA  
mA  
@ 1 µs Cycle Time2  
VCC=2.3 V, VIN=VIH or VIL  
Chip Enabled, IOUT = 0  
Read/Write Operating Supply Current  
@ 85 ns Cycle Time2  
13.0  
VIN = VCC or 0V  
Chip Disabled  
Standby Current3  
ISB1  
450  
nA  
tA= 37oC, VCC = 2.3 V  
VCC = 1.0V, VIN = VCC or 0  
Chip Disabled, tA= 85oC  
Data Retention Current3  
IDR  
1.0  
µA  
1. These limits are the expected operating conditions for this device. Only selected points within this range of conditions  
are specifically tested and guaranteed.  
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current  
required to drive output capacitance expected in the actual system.  
3. The chip is Disabled when CE1# is high or CE2 is low or UB# and LB# are high. The chip is Enabled when CE1# is  
low and CE2 is high.  
(DOC#14-02-036 Rev C ECN#01-0887)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.  
3