MUAC Routing CoProcessor (RCP) Family
Electrical
Switching Characteristics
-35
-40
-50
-70
-90
-12
No Symbol
1a tELEL
1b tELEL
2a tELEH
2b tELEH
Parameter (all times in nanoseconds)
Chip Enable Cycle Time (Other Cycles)
Chip Enable Cycle Time (Compare Cycle)
Chip Enable LOW Pulse Width (Other Cycles)
Chip Enable LOW Pulse Width (Compare Cycle)
Chip Enable HIGH Pulse Width
Min Max Min Max Min Max Min Max Min Max Min Max Notes
40
35
30
25
9
40
40
30
30
10
5
50
50
40
40
10
5
50
70
40
60
10
5
50
90
40
75
10
8
75
120
55
90
10
10
5
3
4
3
4
3
4
5
6
7
tEHEL
tCVEL
tELCX
tELQX
tELQV
Control Input to Chip Enable LOW Setup Time
Control Input to Chip Enable LOW Hold Time
Chip Enable LOW to Outputs Active
5
5
5
6
6
6
7
6
4
4
4
4
4
5
5
5
5
5
5
Chip Enable LOW to Outputs Valid
Register
Memory
30
35
10
35
40
10
40
50
10
40
50
10
40
70
10
50
80
15
8
9
tEHQZ
tDVEL
Chip Enable HIGH to Outputs High-Z
Data to Chip Enable LOW Setup Time
Data from Chip Enable LOW Hold Time
2
4
4
2
4
4
5
0
2
4
4
5
0
2
4
4
5
0
2
4
4
5
0
2
5
5
5
3
10 tELDX
Commercial
Industrial n/a
0
11 tFIVEL
12 tFIVFFV
13 tEHFFV
14 tEHQX
15 tEHQV
16 tMIVEL
17 tEHMX
18 tEHMV
Full In Valid to Chip Enable LOW Setup Time
Full In Valid to Full Flag Valid
5
6
8
8
9
12
25
Chip Enable HIGH to Full Flag Valid
Chip Enable HIGH to Output Change
Chip Enable HIGH to Output Valid
15
15
16
16
16
2
2
2
2
2
2
15
18
22
22
25
30
Match In Valid to Chip Enable LOW Setup
Chip Enable HIGH to Match Flag Change
Chip Enable HIGH to Match Flag Valid
4
2
6
2
8
2
8
2
10
2
12
2
/MF
12
15
42
5
14
15
50
6
15
15
60
8
17
17
n/a
8
20
20
n/a
9
25
25
n/a
12
12
15
16
/MM
19 tELMV
Chip Enable LOW to Match Flag Valid
Match In Valid to Match Flag Valid
20 tMIVMV
/MF
/MM
2
7
7
8
8
9
21 tOEHQZ
22 tOELQV
23 tMIVOEL
24 tFIVOEL
25 tEHRSTL
Output Enable HIGH to Outputs High-Z
10
8
2
10
10
2
10
12
2
10
12
2
10
14
2
Output Enable LOW to Match Address Outputs Valid
Match in Valid to Output Enable LOW
Full in Valid to Output Enable LOW
3
3
3
3
3
4
3
3
3
3
3
4
Chip Enable HIGH to Reset LOW
10
25
10
20
20
2
15
30
15
20
20
2
20
50
20
20
20
2
20
50
20
20
20
2
20
50
20
20
20
2
25
70
25
25
25
2
26 tRSTLRSTH Reset Pulse Width
8
27 tRSTHEL
Reset HIGH to Chip Enable LOW
28 tTIVTCLKH Test Input Valid to TCLK HIGH Setup Time
29 tTCLKHTIX TCLK HIGH to Test Input Hold Time
30 tTCLKLTDOX TCLK LOW to TDO Change
31 tTCLKLTDOV TCLK LOW to TDO Valid
32 tTCLKLTDOZ TCLK LOW to TDO High-Z
9
9
10
20
10
20
10
20
10
20
10
20
15
25
20
20
20
20
20
25
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
-1.0V for a duration of 10ns measured from the 50% amplitude points (see Figure 6) for input-only lines.
Common I/O lines are clamped so that transients cannot fall below -0.5V.
Applies to all cycle types except Compare cycles and Memory Read cycles (memory to DQ).
Applies to Compare cycles (including NEXT).
Control signals are /CS1, /CS2, /W, /AV, DSC, and the AC bus.
With loads specified in Figure 5, Test load A from Table 7.
With loads specified in Figure 5, Test load B from Table 7.
/E should be HIGH during /RESET active to ensure proper device defaults.
Test inputs are the TDI and TMS signals.
10. With output and I/O pins unloaded
11. Pins with internal pull-ups are /RESET, TCLK, TMS, TDI, and /TRST.
28
Rev. 4a
MUSIC [ MUSIC SEMICONDUCTORS ]
