Software Model
MU9C8338A 10/100Mb Ethernet Filter Interface
Chip Registers
The system should decode one unique range of addresses
to produce an individual chip select (/PCS) signal for the
MU9C8338A component. The lowest address in this
application-defined address range is referred to as
CHIP_BASE. Table 16 shows the Chip registers and their
address values.
Table 16: Chip Registers
Name
R/W
R/W
R
Description
Chip Role
Address
Default
0H
CHIPROL
CHIPVER
RSTAT
CHIP_BASE + 1H
CHIP_BASE + 2H
CHIP_BASE + 3H
CHIP_BASE + 4H
Chip Version
Result Status
Result Data
03H
N/A
R
RDAT
R
N/A
Chip Role Register
Result Status Register
The Chip Role register stores the designation of the
MU9C8338A. This register defaults to 0H. The register
must always contain 0H. All other values are reserved.
The Result Status register is used to convey whether the
Result Data register stores any valid result data. Reading
this register resets the /INTR pin if it was asserted because
of result data being processed (after all valid result data is
read).
Table 17: CHIPROL: Chip Role Register Mapping
Name
Bits
Function
Description
Table 19: RSTAT: Result Status Register Mapping
CHIPROL
2:0
Chip
0: Default
All other values
are Reserved
Name
Bits
Description
RDATA
0
1: Result Data available
0: No Result Data
Chip Version Register
The Chip Version register stores the version of the chip.
The value of this read-only register will be incremented
for each subsequent release.
Result Data Register
The Result Data register stores the result of the automatic
SA and DA processing.
Table 18: CHIPVER: Chip Version Register
Mapping
Table 20: RDAT: Result Data Register Mapping
Name
Bits
Description
Name
Bits
Description
Source Port ID
Packet Type
15:10 6-bit Port ID
CHIPVER
4:0
Chip Version
9:8
7
00: Broadcast
01: Multicast
10: Unicast
11: RESERVED
Match Found
0: Match Not Found
1: Match Found
Destination Port ID
6:1
0
6-bit Port ID
Destination Port = Source Port
1: Ports are the same
0: Ports are different
Rev. 0a
15
MUSIC [ MUSIC SEMICONDUCTORS ]
