MU9C8248
PINOUT DIAGRAM
SRMAT
ABORT
VCC
ALE, SRNW
/CS
GND
/RS, /LDS
/WS, /UDS
D0
D1
D2
D3
D4
D5
D6
D7
VCC
D8
D9
GND
D10
D11
D12
D13
D14
D15
VCC
/HBRDY
/HBEN
GND
XSAMAT
GND
XDAMAT
CIP
VCC
/EC
/CM
/FI
/MI
GND
/E
/W
VCC
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
GND
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
MU9C8248
FDDI Interface
(Top View)
/HBDIR
A0
A1
A2
A3
A4
A5
/RESET
/INTEL
/INT
/FULL, /EMPTY
DF7
DF6
DF5
DF4
DF3
DF2
DF1
DF0
DFC
LANCAM Interface:
DQ15–DQ0
(Data Bus, Common I/O, TTL)
The DQ15–DQ0 lines transfer data, commands and status
between the MU9C8248 and the LANCAM. The direction and
nature of the information that flows between the devices are
determined by the states of /CM and /W.
/E
(Chip Enable, Output, TTL)
The /E output enables the LANCAM while LOW and registers
/W, /CM, /EC and DQ15–DQ0 (if /W is LOW) on the falling
edge of /E. If /W is HIGH, data on DQ15–DQ0 from the
LANCAM is valid on the rising edge of /E.
/W
(Write Enable, Output, TTL)
The /W output selects the direction of data flow during a
LANCAM cycle. DQ15–DQ0 write to the LANCAM if /W is LOW
at the falling edge of /E. Read data is output from the LANCAM
to DQ15–DQ0 on the rising edge of /E if /W is HIGH at the
falling edge of /E.
Rev. 2.5
Web
2
DQ9
DQ8
VCC
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DCLK
RCDAT0
RCDAT1
RCDAT2
RCDAT3
RCDAT4
RCDAT5
GND
RCDAT6
RCDAT7
VCC
RCCONT, RCCONTA
RCCONTB
PARITY
MCLK
STRIP
STOPSTRIP
WF
/FFI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PIN DESCRIPTIONS
(/X indicates an active LOW function)
/CM (Data/Command Select, Output, TTL)
The /CM signal determines whether DQ15–DQ0 contain
LANCAM data or commands. /CM is LOW at the falling edge
of /E for Command cycles and HIGH for Data cycles.
/EC (Enable Comparison, Output, TTL)
The /EC signal enables the LANCAM /MF pin to output the
results of a comparison. If /EC is LOW at the falling edge of /E
for a given cycle, the LANCAM /MF output is enabled on the
rising edge of /E. If /EC is HIGH, the LANCAM /MF output is
held HIGH.
/MI (Match Flag, Input, TTL)
The LANCAM /MF pin takes the MU9C8248's /MI input LOW if
a valid match occurs during a Comparison cycle, and /EC was
also LOW at the start of that cycle. The state of the /MI pin
controls branching in the MU9C8248's routines and signalling
to the FDDI chipset.
MUSIC [ MUSIC SEMICONDUCTORS ]
