Instruction Set Descriptions
LIST-XL Family
INSTRUCTION SET DESCRIPTIONS
Instruction: Select Persistent Source (SPS)
Binary Op-Code: 0000 f000 0000 0sss
Instruction: Temporary Command Override (TCO)
Binary Op-Code: 0000 0010 00dd d000
f
Address Field flag
Selected source
ddd
Register selected as source or
destination for only the next
Command Read or Write cycle
sss
Thisinstructionselectsapersistentsourcefordatareads,until
another SPS instruction changes it or a reset occurs. The
default source after reset for Data Read cycles is the
Comparandregister.SettingthepersistentsourcetoM@aaaH
loads the Address register with "aaaH" and the first access to
thatpersistentsourcewillbeataaaH,afterwhichtheARvalue
increments or decrements as set in the Control register.The
SPS M@[AR]instruction does the same except the current
Address Register value is used.
TCOinstructionselectsaregisterasthesourceordestination
for only the next Command Read or Write cycle, so a value
canbeloadedorreadoutoftheregister.SubsequentCommand
ReadorWriteCyclesreverttoreadingtheStatusregisterand
writingtotheInstructiondecoder.AllregistersbuttheNF,PS,
andPDcanbewrittento, andallcanbereadfrom. TheStatus
register is only available via non-TCO Command Read
cycles.ReadingthePSregisteralsooutputstheDeviceIDon
bits 15-4 as shown in Table 11 on page 16.
Instruction: Select Persistent Destination (SPD)
Binary Op-Code: 0000 f001 mmdd dvvv
Instruction: Data Move (MOV)
Binary Op-Code: 0000 f011 mmdd dsss or
0000 f011 mmdd dvss
f
Address Field flag
mm
ddd
vvv
Mask Register select
Selected destination
Validity setting for Memory Location
destinations
f
Address Field flag
mm
ddd
sss
v
Mask Register select
Destination of data
Source of data
Validity setting if destination is a
Memory location
Thisinstructionselectsapersistentdestinationfordatawrites,
which remains until another SPD instruction changes it or a
reset occurs. The default destination for Data Write cycles is
the Comparand register after a reset. When the destination is
theComparandregisterorthememoryarray,thedatawritten
may be masked by either Mask Register 1 or Mask Register
2,sothatonlydestinationbitscorrespondingtobitsinthemask
register set to 0 will be modified. An automatic compare will
occurafterwritingthelastsegmentoftheComparandormask
registers, but not after writing to memory. Setting the
persistentdestinationtoM@aaaHloadstheAddressregister
with"aaaH,"andthefirstaccesstothatpersistentdestination
will be at aaaH, after which the AR value increments or
decrements as set in the Control register. The SPD M@[AR]
instructiondoesthesameexceptthecurrentAddressRegister
value is used.
The MOV instruction performs a 64-bit move of the data in
the selected source to the selected destination. If the source
or destination is aaaH, the Address register is set to "aaaH."
For MOV instructions to or from aaaH or [AR], the Address
registerwillincrementordecrementfromthatvalueafterthe
move completes, as set in the Control register. Data transfers
between the Memory array and the Comparand register may
be masked by either Mask Register 1 or Mask Register 2, in
which case, only those bits in the destination which
correspond to bits in the selected mask register set to 0 will
be changed. A Memory location used as a destination for a
MOVinstructionmaybesettoValidorleftunchanged.Ifthe
source and destination are the same register, no net change
occurs (a NOP).
Rev. 3.1
11
MUSIC [ MUSIC SEMICONDUCTORS ]
