MU9C4480A/L
OPERATIONAL CHARACTERISTICS
Throughout the following, “aaaH” represents a three-digit
hexadecimal number “aaa,” while “bbB” represents a two-
digit binary number “bb.” All memory locations are written
to or read from in 16-bit segments. Segment 0 corresponds to
the lowest order bits (bits 15–0) and Segment 3 corresponds
to the highest order bits (bits 63–48).
instruction, selecting a different source or destination for
data. Subsequent Data Read or Data Write cycles will
access that source or destination until another SPS or SPD
instruction is executed. The currently selected persistent
source or destination can be read back through a TCO PS
or PD instruction. The sources and destinations available
for persistent access are those resources on the 64-bit bus:
Comparand register, Mask Register 1, Mask Register 2, and
the Memory array.
THE CONTROL BUS
Refer to the Block Diagram on page 1 for the following
discussion. The inputs Chip Enable (/E), Write Enable (/W),
Command Enable (/CM), and Enable Daisy Chain (/EC) are
the primary control mechanism for the LANCAM. The /EC
input of the Control bus enables the /MF Match flag output
when LOW and controls the daisy chain operation.
Instructions are the secondary control mechanism. Logical
combinations of the Control Bus inputs, coupled with the
execution of Select Persistent Source (SPS), Select Persistent
Destination (SPD), and Temporary Command Override
(TCO) instructions allow the I/O operations to and from
the DQ15–0 lines to the internal resources, as shown in
Table 3 on page 8.
The default destination for Command Write cycles is the
Instruction decoder, while the default source for Command
Read cycles is the Status register.
Temporary Command Override (TCO) instructions provide
access to the Control register, the Page Address register,
the Segment Control register, the Address register, the Next
Free Address register, and Device Select register. TCO
instructions are only active for one Command Read or Write
cycle after being loaded into the Instruction decoder.
The data and control interfaces to the LANCAM are
synchronous. During a Write cycle, the Control and Data
inputs are registered by the falling edge of /E. When writing
to the persistently selected data destination, the Destination
Segment counter is clocked by the rising edge of /E. During
a Read cycle, the Control inputs are registered by the falling
The Comparand register is the default source and
destination for Data Read and Write cycles. This default
state can be overridden independently by executing a Select
Persistent Source or Select Persistent Destination
Vcc
Vcc
16
DQ 15 –0
/MI
/FI
DQ15–0
/E
/MI
/E
PLD
/W
LANCAM
/MA
/W
/CM
/EC
LAN CAM
/FF
/M F
/CM
/E C
DQ 15 –0
/MI
/FI
/MI
/E
/W
LANCAM
/MA
LAN CAM
/FF
/M F
/CM
/E C
/MI
LANCAM
/MA
/M I
/FI
DQ 15 –0
/MI
LANCAM
/MA
/E
/W
LAN CAM
/FF
/M F
SYST EM FUL L
/CM
/E C
SYS TEM M AT CH
SYSTEM M ATCH
Figure 1a: Vertical Cascading
Figure 1b: External Prioritizing
Rev. 3a
6
MUSIC [ MUSIC SEMICONDUCTORS ]
