MU9C4320L ATMCAM
Control State Descriptions
Set Validity
Address Register Control
Control State:
Mnemonic:
Set Valid Indirect
SET V@[AR]
Control State:
Mnemonic:
Increment Address Register
INC AR
Binary Op Code: XXX XXX 100 000
Binary Op Code: XXX XXX 100 100
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS
Description: Set the Validity bit LOW at the location
pointed to by the contents of the Address register. The
location is set valid and will enter into comparisons during
a Comparison cycle, and will not be written to during a
Write at Next Free Address cycle.
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS
Description: Increments the value held in the Address
register. Used for automatic sequencing through addresses
in the Memory array.
Control State:
Mnemonic:
Decrement Address Register
DEC AR
Control State:
Mnemonic:
Binary Op Code: XXX XXX 100 000
/W: HIGH /AV: HIGH PA:AA: aaa Scope: S
Description: Reads the Validity bit at the location
addressed by the contents of the Address register onto
DQ0. When the validity value is LOW, the location is
valid; when the validity value is HIGH, the location is
empty. DQ31–1 will read as logical 0s.
Read Validity Indirect
RD V@[AR]
Binary Op Code: XXX XXX 100 101
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS
Description: Decrements the value held in the Address
register. Used for automatic sequencing through addresses
in the Memory array.
VP Table Control
Control State:
Mnemonic:
Set VP Table Valid Indirect
SET VP@[AR]
Binary Op Code: XXX XXX 101 000
Control State:
Mnemonic:
Binary Op Code: XXX XXX 100 001
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS
Description: Set the Validity bit HIGH at the location
pointed to by the contents of the Address register. The
location is set empty and will not enter into comparisons
during a Comparison cycle, and may be written to during a
Write at Next Free Address cycle.
Set Empty Indirect
RST V@[AR]
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS
Description: Sets the VP Table bit valid (LOW) at the
location pointed to by the contents of the Address register.
Control State:
Mnemonic:
Read VP Table Indirect
RD VP@[AR]
Binary Op Code: XXX XXX 101 000
/W: HIGH /AV: HIGH PA:AA: aaa Scope: S
Description: Reads the VP Table bit at the location
pointed to by the contents of the Address register onto
DQ0. DQ31–1 will read as logical 0s.
Control State:
Set Empty at Highest-Priority
Matching Location
Control State:
Mnemonic:
Set VP Table Invalid Indirect
RST VP@[AR]
Mnemonic:
Binary Op Code: XXX XXX 100 010
RST V@[HPM]
Binary Op Code: XXX XXX 101 001
/W: LOW /AV: HIGH PA:AA: HPMA Scope: HPD
Description: Set the Validity bit HIGH at the
highest-priority matching location from the previous
Comparison cycle. The location is set empty and will not
enter into comparisons during a Comparison cycle, and
may be written to during a Write at Next Free Address
cycle.
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS
Description: Resets the VP Table bit invalid (HIGH) at
the location pointed to by the contents of the Address
register.
Control State:
Mnemonic:
Set Empty at All Matching Locations
RST V@[AML]
Binary Op Code: XXX XXX 100 011
/W: LOW /AV: HIGH PA:AA: HPMA Scope: AS
Description: Set the Validity bit HIGH at all matching
locations from the previous Comparison cycle. The
locations are set empty and will not enter into comparisons
during a Comparison cycle, and will be written to during a
Write at Next Free Address cycle.
24
Rev. 3
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