MU9C4320L ATMCAM
Pin Descriptions
PIN DESCRIPTIONS
Note:
Signal names that start with a slash (“/”) are active LOW. All signals are 3.3V CMOS level. Never leave inputs floating. The
CAM architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer
to the Electrical Characteristics section for more information.
DQ31–0 (Data Bus, Three-state, Common
Input/Output)
The DQ31–0 lines convey data to and from the
ATMCAM. When the /E input is HIGH the DQ31–0 lines
are held in their high-impedance state. The /W input
determines whether data flows to or from the device on the
DQ31–0 lines. The source or destination of the data is
determined by the AC11–0 lines and the /AV line. During
a Write cycle, data on the DQ31–0 lines is registered by
the falling edge of /E.
AA11–0 (Active Address, Output)
The AA11–0 lines convey the CAM Match address, the
VP Table address, the Next Free address, or Random
Access address, depending on the most recent memory
cycle. The /OE input enables the AA11–0 outputs; when
the /OE input is HIGH, the AA11–0 outputs are in their
high-impedance state; when /OE is LOW the AA11–0
lines are active. In a vertically cascaded system after a
Comparison cycle, Write at Next Free Address cycle or
Read/Write at Highest-Priority match, only the
highest-priority device will enable its AA11–0 lines,
regardless of the state of the /OE input. In the event of a
mismatch in both CAM array and VP Table after a
Compare cycle, or after a Write at Next Free Address
cycle into an already full system, the lowest-priority
device will drive the AA11–0 lines with all 1s. The
AA11–0 lines are latched when /E is LOW, and are free to
change only when /E is HIGH.
AC11–0 (Address/Control Bus, Input)
When Hardware control is selected, the AC11–0 lines
convey address or control information to the ATMCAM,
depending on the state of the /AV input. When /AV is
LOW then AC11–0 carry an address; when /AV is HIGH
AC11–0 carry control information. Data on the AC11–0
lines are registered by the falling edge of /E. When
software control is selected, the state of the AC11–0 lines
does not affect the operation of the device.
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
GND
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
DQ14
DQ15
GND
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
GND
PA3
PA2
PA1
PA0
GND
NC
AA11
AA10
AA9
AA8
GND
AA7
AA6
AA5
AA4
VDD
AA3
AA2
AA1
AA0
GND
/MF
/FF
VDD
/MI
/FI
GND
/MV
/MM
NC
AC11
AC10
AC9
AC8
GND
AC7
AC6
AC5
AC4
VDD
AC3
AC2
AC1
AC0
GND
TDO
TDI
TMS
TCLK
ATMCAM
100-Pin TQFP
(Top View)
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
DQ21
DQ22
DQ23
GND
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
GND
/E
/W
/CS1
/CS2
/OE
GND
/AV
/VB
/RESET
/TRST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Figure 3: ATMCAM Pinout
4
Rev. 3
MUSIC [ MUSIC SEMICONDUCTORS ]
