®
MU9C1965A LANCAM MP
Operational Characteristics
the right or left by issuing a Shift Right or Shift Left
instruction, with the right and left limits for the wrap
around determined by the CAM/RAM partitioning set in
the Control register. During shift rights, bits shifted off the
LSB of the CAM partition will reappear at the MSB of the
CAM partition. Likewise, bits shifted off the MSB of the
CAM partition will reappear at the LSB during shift lefts.
The Memory Array
Memory Organization
The Memory array is organized into 128-bit words with
each word having an additional two validity bits (Skip and
Empty). By default, all words are configured to be 128
CAM cells. However, bits 8–6 of the Control register can
divide each word into a CAM field and a RAM field. The
RAM field can be assigned to the least-significant or
most-significant portion of each entry. The CAM/RAM
partitioning is allowed on 32-bit boundaries, permitting
selection of the configurations shown in Table 9 on page
24, bits 8–6 (e.g., 001 sets the 96 MSBs to CAM and the
32 LSBs to RAM). Memory Array bits designated as
RAM can be used to store and retrieve data associated
with the CAM content at the same memory location.
Mask Registers (MR1, MR2)
The Mask registers can be used in two different ways,
either to mask compares or to mask data writes and moves.
Either mask register can be selected in the Control register
to mask every compare, or selected by instructions to
participate in data writes or moves to and from Memory. If
a bit in the selected mask register is set to a 0, the
corresponding bit in the Comparand register will enter into
a masked compare operation. If a Mask bit is a 1, the
corresponding bit in the Comparand register will not enter
into a masked compare operation. Bits set to 0 in the mask
register cause corresponding bits in the destination register
or memory location to be updated when masking data
writes or moves, while a bit set to 1 will prevent that bit in
the destination from being changed.
Memory Access
There are two general ways to get data into and out of the
memory array: directly or by moving the data via the
Comparand or mask registers.
The first way, through direct reads or writes, is set up by
issuing a Set Persistent Destination (SPD) or Set Persistent
Source (SPS) command. The addresses for the direct
access can be directly supplied, supplied from the Address
register, supplied from the Next Free Address register, or
supplied as the Highest-Priority Match address.
Additionally, all the direct writes can be masked by either
mask register.
Either the Foreground or Background MR1 can be set
active, but after a reset, the Foreground MR1 is active by
default. MR2 incorporates a sliding mask, where the data
can be replicated one bit at a time to the right or left with
no wraparound by issuing a Shift Right or Shift Left
instruction. The right and left limits are determined by the
CAM/RAM partitioning set in the Control register. For a
Shift Right the upper limit bit is replicated to the next
lower bit, while for a Shift Left the lower limit bit is
replicated to the next higher bit.
The second way is to move data via the Comparand or
mask registers. This is accomplished by issuing Data
Move commands (MOV). Moves using the Comparand
register can also be masked by either of the mask registers.
/E
/W
/CM
/EC
DQ31-0
DATA OUT
Figure 5: Read Cycle
Rev. 2
13
MUSIC [ MUSIC SEMICONDUCTORS ]
