WidePort LANCAM® Family
INSTRUCTION SET SUMMARY Continued
CYCLETYPE
Command Read
CYCLE
LENGTH
Data Write
Data Read
Command Write
MOV reg, reg (except L-70)
Comparand register
(not last segment)
Mask register
Short
TCO reg (except CT)
TCO CT (non-reset, HMA invalid)
SPS, SPD, SFR
(not last segment)
SBR, RSC, NOP
SFT (A)
Comparand register
Mask register
MOV reg, reg (L-70)
MOV reg, mem
TCO CT (reset)
VBC (NFA invalid)
SFT (L)
Memory array
(NFA invalid)
Status register or
16-bit register
Medium
Long
Memory array
Memory array
(NFA valid)
Comparand register
(last segment)
Mask register
(last segment)
MOV mem, reg
TCO CT (non-reset, HMA valid)
CMP
SFF
VBC (NFA valid)
Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics
Section under the tELEH parameter. For two cycle TCO reads of a register’s contents, the first cycle (Command
Write TCO) is short, and the second cycle (Command read) is medium.
Table 8: Instruction Cycle Lengths
REGISTER BIT ASSIGNMENTS
15
14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
RST Match Flag Full Flag Translation
CAM/RAM Part.
Comp. Mask AR Inc/Dec
Mode
64 CAM/0 RAM = 000
48 CAM/16 RAM = 001
32 CAM/32 RAM = 010
16 CAM/48 RAM = 011
48 RAM/16 CAM = 100
32 RAM/32 CAM = 101
16 RAM/48 CAM = 110
No Change = 111
None = 00
MR1 = 01
MR2 = 10
No Change
= 11
Increment
= 00
Decrement
= 01
Disable
= 10
No Change
= 11
R
E
S
E
T
=
0
Enable
=00
Disable
= 01
No Change
= 11
Enable
= 00
Disable
= 01
Input Not
Translated
= 00
Standard Mode
= 00
Enhanced Mode
= 01
Reserved
= 10
No Change
= 11
Input
No Change Translated
= 11
= 01
No Change
= 11
Note: D15 reads back as 0.
Table 9: Control Register Bit Assignments
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
0
0
0
0
0
0
Src.
Count
Start
Limit
Dest.
Count
Start
Limit
Dest. Set
Count Source
Src. Load
Count Dest.
End Seg.
Limit Count
= 0
Dest. Load
Seg. Src.
Count Seg.
Value Count
= 0
Src.
Seg.
Count
Value
Set
Dest.
Seg.
Limits
= 0
End
Seg.
Limit Limits
= 0
No
No
No
No
Chng.
= 1
Chng.
= 1
Chng.
= 1
Chng.
= 1
Note: D15, D10, D5, and D2 read back as 0s. Reserved locations D14, D12, D9, D7, D4, and D1 should always
be set to 0.
Table 10: Segment Control Register Bit Assignments
21
Rev. 2
MUSIC [ MUSIC SEMICONDUCTORS ]
