Pin Descriptions
LANCAM B Family
PIN DESCRIPTIONS
Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW.
Inputs should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good
layout and bypassing techniques. Refer to the DC Electrical Characteristics on page 25 for more information.
NC
NC
GND
DQ4
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
NC
/MA
/MI
/MF
GND
GND
/RESET
VCC
VCC
TEST1
/E
GND
DQ4
1
33
32
31
30
29
28
27
26
25
24
23
/MA
2
/MI
DQ5
DQ5
3
/MF
VCC
VCC
TEST2
GND
GND
GND
VCC
VCC
TEST2
GND
GND
DQ6
4
GND
/RESET
VCC
VCC
TEST1
/E
5
44-Pin LQFP
(Top View)
64-Pin LQFP
(Top View)
6
9
10
11
7
8
9
GND
DQ6
DQ7
VCC
NC
12
13
14
15
16
37
36
35
34
33
/W
DQ7
VCC
10
11
/W
GND
GND
GND
NC
NC
Figure 2: 44-Pin LQFP
/E (Chip Enable, Input, TTL)
Figure 3: 64-Pin LQFP
The /E input enables the device while LOW. The falling
edge registers the control signals /W, /CM, and /EC. The
rising edge locks the daisy chain, turns off the DQ pins,
and clocks the Destination and Source Segment counters.
The four cycle types enabled by /E are shown in Table 1.
The /EC signal also enables the /MF–/MI daisy chain,
which serves to select the device with the highest-priority
match in a string of LANCAMs. Table 4 explains the
effect of the /EC signal on a device with or without a
match in both Standard and Enhanced modes. /EC must be
HIGH during initialization.
Table 1: I/O Cycles
DQ15–0 (Data Bus, I/O, TTL)
/W
/CM
LOW
HIGH
LOW
HIGH
Cycle Type
The DQ15–0 lines convey data, commands, and status to
and from the LANCAM. /W and /CM control the direction
and nature of the information that flows to or from the
device. When /E is HIGH, DQ15–0 go to HIGH-Z.
LOW
LOW
HIGH
HIGH
Command Write Cycle
Data Write Cycle
Command Read Cycle
Data Read Cycle
/MF (Match Flag, Output, TTL)
/W (Write Enable, Input, TTL)
The /MF output goes LOW when one or more valid
matches occur during a compare cycle. /MF becomes valid
after /E goes HIGH on the cycle that enables the daisy
chain (on the first cycle that /EC is registered LOW by the
previous falling edge of /E; see Figure 9 on page 14). In a
daisy chain, valid match(es) in higher priority devices are
passed from the /MI input to /MF. If the daisy chain is
enabled but the match flag is disabled in the Control
register, the /MF output only depends on the /MI input of
the device (/MF=/MI). /MF is HIGH if there is no match
or when the daisy chain is disabled (/E goes HIGH when
/EC was HIGH on the previous falling edge of /E). The
System Match flag is the /MF pin of the last device in the
daisy chain. /MF is reset when the active configuration
register set is changed.
The /W input selects the direction of data flow during a
device cycle. /W LOW selects a Write cycle and /W HIGH
selects a Read cycle.
/CM (Data/Command Select, Input, TTL)
The /CM input selects whether the input signals on
DQ15–0 are data or commands. /CM LOW selects
Command cycles and /CM HIGH selects Data cycles.
/EC (Enable Daisy Chain, Input, TTL)
The /EC signal performs two functions. The /EC input
enables the /MF output to show the results of a
comparison, as shown in Figure 9 on page 14. If /EC is
LOW at the falling edge of /E in a given cycle, the /MF
output is enabled. Otherwise, the /MF output is held
HIGH.
Rev. 5.1
3
MUSIC [ MUSIC SEMICONDUCTORS ]
