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MU9C1480BF-90TAI 参数 Datasheet PDF下载

MU9C1480BF-90TAI图片预览
型号: MU9C1480BF-90TAI
PDF下载: 下载PDF文件 查看货源
内容描述: [Content Addressable SRAM, 1KX64, 90ns, CMOS, PQFP44]
分类和应用: 双倍数据速率静态存储器内存集成电路
文件页数/大小: 32 页 / 236 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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LANCAM B Family  
Operational Characteristics  
/E  
/W  
/CM  
/EC  
DQ15–0  
Figure 8: Write Cycle  
ASSOCIATED DATA  
READ CYCLE  
COMPARAND WRITE  
CYCLE  
STATUS READ  
CYCLE  
/E  
/CM  
/W  
DQ15–0  
DATA  
DATA  
DATA  
/EC  
/MF  
MATCH FLAG VALID  
/MA, /MM  
/MA AND /MM FLAGS UPDATED  
Figure 9: Cycle-to-Cycle Timing Example  
I/O Cycles  
The LANCAM supports four basic I/O cycles: Data Read,  
Data Write, Command Read, and Command Write. The  
states of the /W and /CM control inputs determine the type  
of cycle. These signals are registered at the beginning of a  
cycle by the falling edge of /E. Table 1 on page 3 shows  
how the /W and /CM signals select the cycle type.  
cycle prior to any cycle that requires a locked daisy chain,  
such as a Status register or associated data read after a  
match. If there is no match in Standard mode, the output  
buffers stay High-Z, and the daisy chain must be unlocked  
by taking /EC HIGH during  
a NOP or other  
non-functioning cycle, as indicated in Table 4 on page 12.  
Figure 9 on page 14 shows how the internal /EC timing  
holds the daisy chain locking effect over into the next  
cycle. In Enhanced mode, this NOP is not needed before  
data or command writes following a non-matching  
compare, as indicated by Table 4 on page 12. A  
single-chip system does not require daisy-chained match  
flag operation, hence /EC could be tied HIGH and the  
/MA pin or flag in the Status register used instead of /MF,  
allowing access to the device regardless of the match  
condition.  
During Read cycles, the DQ15–0 outputs are enabled after  
/E goes LOW. During Write cycles, the data or command  
to be written is captured from DQ15–0 at the beginning of  
the cycle by the falling edge of /E. Figure 10 on page 15  
and Figure 7 on page 13, show Read and Write cycles  
respectively. Figure 8 on page 14, shows typical  
cycle-to-cycle timing with the Match flag valid at the end  
of the Comparand Write. Data writes and reads to the  
comparand, Mask registers, or memory occur in one to  
four 16-bit cycles, depending on the settings in the  
Segment Control register. The Compare operation  
automatically occurs during Data writes to the Comparand  
or Mask registers when the destination segment counter  
reaches the end count set in the Segment Control register.  
If there was a match, the second cycle reads status or  
associated data, depending on the state of /CM. For  
cascaded devices, /EC needs to be LOW at the start of the  
The minimum timings for the /E control signal are given  
in Table 9 on page 27. Note that at minimum timings the  
/E signal is non-symmetrical and that different cycle types  
have different timing requirements, as given in Table 6 on  
page 22.  
14  
Rev. 5.2  
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