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MU9C1480B-70TAC 参数 Datasheet PDF下载

MU9C1480B-70TAC图片预览
型号: MU9C1480B-70TAC
PDF下载: 下载PDF文件 查看货源
内容描述: LANCAM B族 [LANCAM B Family]
分类和应用: 存储内存集成电路静态存储器双倍数据速率局域网
文件页数/大小: 32 页 / 265 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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Switching  
LANCAM B Family  
Switching Characteristics  
Table 9: Switching Characteristics  
Cycle Time  
-50  
-70  
-90  
No.  
Symbol  
Parameter  
Min. Max. Min. Max. Min. Max Notes  
1
t
Chip Enable Compare Cycle Time  
50  
70  
90  
ELEL  
Short Cycle  
15  
30  
45  
5
15  
35  
55  
15  
25  
50  
75  
15  
4
4
4
t
2
Chip Enable LOW Pulse Width  
Chip Enable HIGH Pulse Width  
Medium Cycle  
Long Cycle  
ELEH  
3
4
5
6
t
EHEL  
t
Control Input to Chip Enable LOW Setup Time  
Control Input from Chip Enable LOW Hold Time  
Chip Enable LOW to Outputs Active  
2
10  
3
2
10  
3
2
10  
3
5
5
6
CVEL  
t
ELCX  
t
ELQX  
Register Read  
Chip Enable LOW to Outputs Valid  
Memory Read  
30  
40  
10  
30  
52  
10  
50  
75  
15  
4,6  
4,6  
7
t
7
ELQV  
8
t
Chip Enable HIGH to Outputs HIGH-Z  
Data to Chip Enable LOW Setup Time  
Data from Chip Enable LOW Hold Time  
Full In Valid to Chip Enable LOW Setup Time  
Full In Valid to Full Flag Valid  
3
2
3
2
3
2
EHQZ  
9
t
DVEL  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
t
10  
0
10  
0
10  
0
ELDX  
t
FIVEL  
t
5
5
7
FIVFFV  
t
Chip Enable LOW to Full Flag Valid  
Match in Valid to Chip Enable LOW Setup Time  
Chip Enable HIGH to /MF, /MA, /MM Invalid  
Match In Valid to /MF Valid, /MA, /MM  
Chip Enable HIGH to /MF Valid  
35  
50  
75  
ELFFV  
t
0
0
0
0
0
0
MIVEL  
t
EHMFX  
t
4
5
7
MIVMFV  
t
16  
18  
16  
18  
25  
25  
EHMFV  
EHMXV  
t
Chip Enable HIGH to /MA and /MM Valid  
Reset LOW Pulse Width  
t
50  
100  
100  
8
RLRH  
Notes:  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
9.  
1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (see Figure 12 on page 26).  
Common I/O lines are clamped, so that signal transients can not fall below -0.5 Volts.  
Over ambient operating temperature range and Vcc(min.) to Vcc(max.).  
See Table 6 on page 22.  
Control signals are /W, /CM, and /EC.  
With load specified in Figure 11 on page 26, Test Load A.  
With load specified in Figure 11 on page 26, Test Load B.  
/E must be HIGH during this period to ensure accurate default values in the configuration registers.  
With output and I/O pins unloaded.  
10. TEST1 and/or TEST2 may not be implemented on all versions of these products.  
Rev. 5.1  
27