LANCAM A/L series (not recommended for new designs)
Instruction Set Descriptions
INSTRUCTION SET DESCRIPTIONS
Notes: Instruction cycle lengths given in Table 6 on page 22. If f=1, the instruction requires an absolute address to be supplied on the
following cycle as a Command write. The value supplied on the second cycle of the instruction updates the address register. After
operations involving M@[AR] or M@aaaH, the Address register increments or decrements depending on the setting in the Control
register.
Instruction: Select Persistent Source (SPS)
Binary Op-Code: 0000 f000 0000 0sss
Instruction: Temporary Command Override (TCO)
Binary Op-Code: 0000 0010 00dd d000
f
sss
Address Field flag
Selected source
ddd
Register selected as source or
destination for only the next
Command Read or Write cycle
This instruction selects a persistent source for data reads,
until another SPS instruction changes it or a reset occurs.
The default source after reset for Data Read cycles is the
Comparand register. Setting the persistent source to
M@aaaH loads the Address register with “aaaH” and the
first access to that persistent source is at aaaH, after which
the AR value increments or decrements as set in the
Control register. The SPS M@[AR] instruction does the
same except the current Address Register value is used.
The TCO instruction selects a register as the source or
destination for only the next Command Read or Write
cycle, so a value can be loaded or read out of the register.
Subsequent Command Read or Write cycles revert to
reading the Status register and writing to the Instruction
decoder. All registers but the NF, PS, and PD can be
written to, and all can be read from. The Status register is
only available through non-TCO Command Read cycles.
Reading the PS register also outputs the Device ID on bits
15–4 as shown in Persistent Source Register Bits on page
25.
Instruction: Select Persistent Destination (SPD)
Binary Op-Code: 0000 f001 mmdd dvvv
f
Address Field flag
Instruction: Data Move (MOV)
Binary Op-Code: 0000 f011 mmdd dsss or
0000 f011 mmdd dvss
mm
ddd
vvv
Mask Register select
Selected destination
Validity setting for Memory Location
destinations
f
Address Field flag
mm
ddd
sss
v
Mask Register select
Destination of data
Source of data
Validity setting if destination is a
Memory location
This instruction selects a persistent destination for data
writes, which remains until another SPD instruction
changes it or a reset occurs. The default destination for
Data Write cycles is the Comparand register after a reset.
When the destination is the Comparand register or the
Memory array, the data written may be masked by either
Mask Register 1 or Mask Register 2, so that only
destination bits corresponding to bits in the Mask register
set to 0 are modified. An automatic compare occurs after
writing the last segment of the Comparand or Mask
registers, but not after writing to Memory. Setting the
persistent destination to M@aaaH loads the Address
register with “aaaH,” and the first access to that persistent
destination is at aaaH, after which the AR value
increments or decrements as set in the Control register.
The SPD M@[AR] instruction does the same except the
current Address Register value is used.
The MOV instruction performs a 64-bit move of the data
in the selected source to the selected destination. If the
source or destination is aaaH, the Address register is set to
“aaaH.” For MOV instructions to or from aaaH or [AR],
the Address register increments or decrements from that
value after the move completes, as set in the Control
register. Data transfers between the Memory array and the
Comparand register may be masked by either Mask
Register 1 or Mask Register 2, in which case, only those
bits in the destination that correspond to bits in the
selected Mask register set to 0 are changed. A Memory
location used as a destination for a MOV instruction may
be set to Valid or left unchanged. If the source and
destination are the same register, no net change occurs (a
NOP).
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Rev. 1
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