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MU9C4480L-90DC 参数 Datasheet PDF下载

MU9C4480L-90DC图片预览
型号: MU9C4480L-90DC
PDF下载: 下载PDF文件 查看货源
内容描述: LANCAM A / L系列 [LANCAM A/L series]
分类和应用: 局域网
文件页数/大小: 32 页 / 332 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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Operational Characteristics  
LANCAM A/L series (not recommended for new designs)  
set in the Control register. During shift rights, bits shifted  
off the LSB of the CAM partition reappear at the MSB of  
the CAM partition. Likewise, bits shifted off the MSB of  
the CAM partition reappear at the LSB during shift lefts.  
The Memory Array  
Memory Organization  
The Memory array is organized into 64-bit words with  
each word having an additional two validity bits. By  
default, all words are configured to be 64 CAM cells.  
However, bits 8–6 of the Control register can divide each  
word into a CAM field and a RAM field. The RAM field  
can be assigned to the least-significant or most-significant  
portion of each entry.  
Mask Registers (MR1, MR2)  
The Mask registers can be used in two different ways:  
either to mask compares or to mask data writes and moves.  
Either Mask register can be selected in the Control register  
to mask every compare, or selected by instructions to  
participate in data writes or moves to and from Memory. If  
a bit in the selected Mask register is set to a 0, the  
corresponding bit in the Comparand register enters into a  
masked compare operation. If a Mask bit is a 1, the  
corresponding bit in the Comparand register does not enter  
into a masked compare operation. Bits set to 0 in the Mask  
register cause corresponding bits in the destination register  
or memory location to be updated when masking data  
writes or moves, while a bit set to 1 prevents that bit in the  
destination from being changed.  
The CAM/RAM partitioning is allowed on 16-bit  
boundaries, permitting selection of the configuration  
shown in Control Register Bits on page 23, bits 8–6 (e.g.,  
“001” sets the 48 MSBs to CAM and the 16 LSBs to  
RAM). Memory Array bits designated as RAM can be  
used to store and retrieve data associated with the CAM  
content at the same memory location.  
Memory Access  
There are two general ways to get data into and out of the  
Memory array: directly or by moving the data by means of  
the Comparand or Mask registers.  
Either the Foreground or Background MR1 can be set  
active, but after a reset, the Foreground MR1 is active by  
default. MR2 incorporates a sliding mask, where the data  
can be replicated one bit at a time to the right or left with  
no wrap-around by issuing a Shift Right or Shift Left  
instruction. The right and left limits are determined by the  
CAM/RAM partitioning set in the Control register. For a  
Shift Right the upper limit bit is replicated to the next  
lower bit, while for a Shift Left the lower limit bit is  
replicated to the next higher bit.  
The first way, through direct reads or writes, is set up by  
issuing a Set Persistent Destination (SPD) or Set Persistent  
Source (SPS) command. The addresses for the direct  
access can be supplied directly; supplied from the Address  
register, supplied from the Next Free Address register, or  
supplied as the Highest-Priority Match address.  
Additionally, all the direct writes can be masked by either  
Mask register.  
The second way is to move data by means of the  
Comparand or Mask registers. This is accomplished by  
issuing Data Move commands (MOV). Moves using the  
Comparand register can also be masked by either of the  
Mask registers.  
/E  
/W  
/CM  
/EC  
DQ15-0  
DATA OUT  
Figure 6: Read Cycle  
Rev. 1  
13  
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