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MU9C1480A-70DC 参数 Datasheet PDF下载

MU9C1480A-70DC图片预览
型号: MU9C1480A-70DC
PDF下载: 下载PDF文件 查看货源
内容描述: LANCAM A / L系列 [LANCAM A/L series]
分类和应用: 存储内存集成电路静态存储器双倍数据速率局域网
文件页数/大小: 32 页 / 332 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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LANCAM A/L series (not recommended for new designs)  
Register Bit Assignments  
Next Free Address Bits  
Device  
Bit(s)  
15:8  
7:0  
Name  
PA7–0  
NF7-0  
PA6-0  
NF8-0  
PA5–0  
NF9-0  
PA4-0  
NF10-0  
PA3–0  
NF11-0  
Description  
Page Address  
3480A/L  
Next Free Address  
Page Address  
15:9  
8:0  
5480A/L  
1480A/L  
2480A/L  
4480A/L  
Next Free Address  
Page Address  
15:10  
9:0  
Next Free Address  
Page Address  
15:11  
10:0  
15:12  
11:0  
Next Free Address  
Page Address  
Next Free Address  
Note: The Next Free Address register is read only, and is accessed by performing a Command Read cycle immediately following a TCO  
NF instruction.  
Status Register Bits  
Device  
Bit(s)  
31  
Name  
/FL  
Description  
0 = Internal CAM Full  
0 = Internal Multiple Match  
30  
/MM  
VB1-0  
All  
29:28  
00 = Valid  
10 = Skip  
01 = Empty  
11 = RAM  
27  
26:16  
15:11  
10:9  
8:1  
0
Reserved  
PA15-5  
PA4-0  
0
Page Address (second read)  
Page Address (first read)  
Reserved  
3480A/L  
5480A/L  
AM7-0  
0
Match Address  
27  
Reserved  
26:16  
15:11  
10  
PA15-5  
PA4-0  
0
Page Address (second read)  
Page Address (first read)  
Reserved  
9:1  
AM8-0  
0
Match Address  
27  
Reserved  
26:16  
15:11  
10:1  
27:16  
15:12  
11:1  
27:16  
15:13  
12:1  
0
PA15–5  
PA4–0  
AM9–0  
PA15–4  
PA3–0  
AM10–0  
PA14–3  
PA2–0  
AM11–0  
/MA  
Page Address (second read)  
Page Address (first read)  
Match Address  
1480A/L  
2480A/L  
Page Address (second read)  
Page Address (first read)  
Match Address  
Page Address (second read)  
Page Address (first read)  
Match Address  
4480A/L  
All  
Match Flag  
Note: The Status register is read only, and is accessed by performing Command Read cycles. On the first cycle, bits 15–0 are output,  
and if a second Command Read cycle is issued immediately after the first Command Read cycle, bits 31–16 are output.  
24  
Rev. 1  
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