ADC-207
7-Bit, 20MHz, CMOS Flash A/D Converters
OUTPUT CODING
(+REFERENCE = +5.12V, –REFERENCE = ground, MIDPOINT = no connection)
NOTE: The reference should be held to ±0.1% accuracy or better. Do not use the +5V
power supply as a reference input without precision regulation and high frequency
decoupling.
Values shown here are for a +5.12V reference. Scale other references proportionally.
Calibration equipment should test for code changes at the midpoints between these
center values shown in Table 1. For example, at the half-scale major carry, set the
input to 2.54V and adjust the reference until the code flickers equally between 63 and
64. Note also that the weighting for the comparator resistor network leaves the first
and last thresholds within 1/2LSB of the end points to adjust the code transition to the
proper midpoint values.
CLOCK
Æ1
AUTO
ZERO
Æ2
SAMPLE
N
Æ1
AUTO
ZERO
Æ2
SAMPLE
N+1
Æ1
AUTO
ZERO
Æ2
SAMPLE
N+2
OUTPUT
DATA
N DATA
N+1 DATA
17ns max.
17ns max.
TIMING DIAGRAM
Table 1. ADC-207 Output Coding
Analog Input
(Center Value)
0.00V
+0.04V
+1.28V
+2.52V
+2.56V
+2.60V
+3.84V
+5.08V
+5.12V
Code
Zero
+1LSB
+1/4FS
+1/2FS – 1LSB
+1/2FS
+1/2FS + 1LSB
+3/4FS
+FS
Overflow
Overflow
0
0
0
0
0
0
0
0
1
1
MSB
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
2
3
4
5
6
7
LSB
0
1
0
1
0
1
0
1
1
Decimal
0
1
32
63
64
65
96
127
255*
Hexadecimal
(Incl. 0V)
00
01
20
3F
40
41
60
7F
FF
*Note that the overflow code does not clear the data bits.
ADC-207 OPERATION
The ADC-207 uses a switched capacitor scheme in which there is an auto-
zero phase and a sampling phase. See
Figure 1 and Timing Diagram. The ADC-207 uses a single clock input.
When the clock is at a high state (logic 1), the ADC-207 is in the auto-zero
phase (Ø1). When the clock is at a low state (logic 0), the ADC-207 is in
the sampling phase (Ø2). During phase 1, the 128 comparator outputs are
shorted to their inputs through CMOS switches. This serves the purpose
of bringing the inputs and outputs to the transition levels of the respective
comparators. The inputs to the comparators are also connected to 128
sampling capacitors. The other end of the 128 capacitors are also shorted
to 128 taps of a resistor ladder, via CMOS switches. Therefore, during
phase 1 the sampling capacitors are charged to the differential voltage
between a resistor tap and its respective comparator transition voltage.
This eliminates offset differences between comparators and yields better
temperature performance. During phase 2 (Ø2) the input voltage is applied to
the 128 capacitors, via CMOS switches. This forces the comparators to trip
either high or low. Since the comparators during phase 1 were sitting at their
transition point, they can trip very quickly to the correct state. Also during
phase 2, the outputs of the comparators are loaded into internal latches
which in turn feed a128-to-7 encoder. When going back into phase 1, the
output of the encoder is loaded into an output latch. This latch then feeds the
3-state output buffer.
This means that the ADC-207 is of pipeline design. To do a single
conversion, the ADC-207 requires a positive pulse followed by a negative
pulse followed by a positive pulse. Continuous conversion requires one
cycle/sample (one positive pulse and one negative pulse). The 3-state
buffer has two enable lines, CS1 and CS2. Table 2 shows the truth table
for chip select signals. CS1 has the function of enabling/disabling bits 1
through 7. CS2 has the function of enabling/disabling bits 1 through 7 and
the overflow bit. Also, a full-scale input produces all ones, including the
overflow bit at the output. The ADC-207 has an adjustable resistor ladder
string. The top end, idle point, and bottom end are brought out for use with
applications circuits.
These pins are called +REFERENCE, MIDPOINT and –REFERENCE,
respectively. In typical operation +REFERENCE is tied to +5V, –REFERENCE
is tied to ground, and MIDPOINT is bypassed to ground. Such a configura-
tion results in a 0 to +5V input voltage range. The MIDPOINT pin can also
be tied to a +2.5V source to further improve integral linearity. This is usually
not necessary unless better than 7-bit linearity is needed.
Table 2. Chip Select Truth Table
CS1
0
1
0
1
CS2
0
0
1
1
Bits 1-7
3-State Mode
3-State Mode
Data Outputed
3-State Mode
Overflow Bit
3-State Mode
3-State Mode
Data Outputed
Data Outputed
NOTE: Reduce the sample time (sample pulse) to 12ns to improve performance
above 20MHz. Such a configuration will closely resemble an ideal sampler.
www.murata-ps.com
Technical enquiries
email: sales@murata-ps.com, tel:
+1 508 339 3000
MDA_ADC-207.B01
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