MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
LAYOUT RECOMMENDATION
GND
1. Place high current paths (GND, IN, and SW)
very close to the device with short, direct and
wide traces.
E 1 C
C1E
R3
C3
C1D
2. Two-layer IN copper layers are required to
achieve better performance. Place at least
one 0.1uF-1uF 0603 or 0402 decoupling input
capacitor on each side of the IC. The input
capacitors should be placed as close to the
IN and GND pins as possible (maximum 2mm
edge-to-edge distance is allowed). Multiple
vias with 18mil diameter and 8mil hole-size
are required to be placed under the device
and near input capacitors. These vias can
help to reduce the parasitic inductance and
optimize the thermal dissipation.
PGND
PGND
BST
VCC
PG
SW
SW
SW
SW
AGND
SS
6 C
3 R
FB
PGND
PGND
FREQ
EN
C1B
3 R
C1A
R3
C2
GND
VIN
VOUT
Top Layer
3. Put a decoupling capacitor as close to the
VCC and AGND pins as possible.
4. Keep the switching node (SW) plane as small
as possible and far away from the feedback
network.
GND
5. Place the external feedback resistors next to
the FB pin. Make sure that there are no vias
on the FB trace. The feedback resistors
should refer to AGND instead of PGND.
6. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
7. Recommend strongly a four-layer layout to
improve thermal performance.
Inner1 Layer
VIN
BST
IN
RFREQ
C1B C1C C1D C1E
C1A
C3
L1
SW
VOUT
FREQ
R5
C4
R4
C2
R1
MPQ8632
EN
MPQ8632H
FB
SS
VCC
C5
R3
R2
C6
PG
AGND
PGND
Figure 55—Schematic for PCB Layout
GND
Guideline
8
7
6
5
4
3
2
1
VIN
VIN
SW
SW
CIN
CIN
CIN
CIN
PGND
PGND
PGND
PGND
To Inductor
Inner2 Layer
Figure 56—Recommend Input Capacitor
Placement for 16-Pin QFN 3mmx4mm
Package Part, including MPQ8632-4/6/8/10/12
and MPQ8632H-10.
MPQ8632 Rev.1.24
8/28/2013
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