MPQ4559 – 1.5A, 2MHz, 55V STEP-DOWN CONVERTER AEC-Q100 QUALIFIED
PIN FUNCTIONS
QFN SOIC8
Pin # Pin #
Name Description
Switch Node. Output from the high-side switch. A low VF Schottky rectifier to ground
is required. The rectifier must be close to the SW pins to reduce switching spikes.
1, 2
3
1
2
3
SW
EN
Enable Input. Pull this pin below the specified threshold to shutdown the chip. Pull it
up above the specified threshold or leaving it floating to enable the chip.
Compensation. Output of the GM error amplifier. Control loop frequency
compensation is applied to this pin.
4
COMP
Feedback. Input to the error amplifier. Sets the regulator voltage by comparing the
tap of an external resistive divider connected between the output and GND to the
internal +0.8V reference.
5
4
FB
GND, Ground. Connect as close as possible to the output capacitor and avoid the high-
Exposed current switch paths. Connect exposed pad to GND plane for optimal thermal
6
7
5
6
7
8
pad
performance.
Switching Frequency Program Input. Connect a resistor from this pin to ground to set
the switching frequency.
FREQ
Input Supply. This supplies power to all the internal control circuitry, both BS
regulators, and the high-side switch. Place a decoupling capacitor to ground close to
this pin to minimize switching spikes.
8, 9
10
VIN
Bootstrap. Positive power supply for the internal floating high-side MOSFET driver.
Connect a bypass capacitor between this pin and SW pin.
BST
MPQ4559 Rev. 1.01
5/24/2016
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
4
MPS [ MONOLITHIC POWER SYSTEMS ]
