MP20041-DUAL, ULTRA LOW NOISE, HIGH PSRR, 300mA LINEAR REGULATOR
APPLICATION INFORMATION
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Power Dissipation
The power dissipation for any package depends
on the thermal resistance of the case and circuit
board, the temperature difference between the
junction and ambient air, and the rate of airflow.
The power dissipation across the device can be
represented by the equation:
P = (VIN - VOUT) ×IOUT
0.1
The allowable power dissipation can be
calculated using the following equation:
0
50
100
150
200
250
300
OUTPUT CURRENT(MA)
P(MAX) = (TJunction - TAmbient) / θJA
Figure 2—Relationship between ESR and
LDO Stability
Where (TJunction - TAmbient) is the temperature
difference between the junction and the
surrounding environment, θJA is the thermal
resistance from the junction to the ambient
environment. Connect the GND pin of MP20041
to ground using a large pad or ground plane
helps to channel heat away.
Reverse Current Path
The PMOS used in the MP20041 has an inherent
diode connected between input and output (see
Figure3). If VOUT - VIN is more than a diode-drop,
this diode gets forward biased and starts to
conduct. To avoid misoperation, an external
Schottky connected in parallel with the internal
parasitic diode prevents it from being turned on
by limiting the voltage drop across it to about
0.3V (see Figure 4).
Input Capacitor Selection
Using a capacitor whose value is >0.47µF on the
MP20041 input and the amount of capacitance
can be increased without limit. Larger values will
help improve line transient response with the
drawback of increased size. Ceramic capacitors are
preferred, but tantalum capacitors may also suffice.
VIN
VOUT
Output Capacitor Selection
The MP20041 is designed specifically to work
with very low ESR ceramic output capacitor in
space-saving and performance consideration. A
ceramic capacitor in the range of 0.47µF and
10µF, and with ESR lower than 1.2Ω is suitable
for the MP20041 application circuit. Output
capacitor of larger values will help to improve
load transient response and reduce noise with
the drawback of increased size.
Figure 3—Inherent Diode Connected between
Each Regulator Input and Output
Figure 4—External Schottky Diode Connected
in Parallel with the Internal Parasitic Diode
MP20041 Rev. 1.0
1/17/2013
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