MP1921A―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
ABSOLUTE MAXIMUM RATINGS (1)
Recommended Operating Conditions (3)
Supply Voltage (VDD) ....................... 9.0V to 18V
SW Voltage (VSW) .......................-1.0V to +100V
SW slew rate .....................................<50V/nsec
Operating Junction Temp. (TJ)..-40°C to +125°C
Supply Voltage (VDD).....................-0.3V to +20V
SW Voltage (VSW) .......................-5.0V to +105V
BST Voltage (VBST) .....................-0.3V to +120V
BST to SW....................................-0.3V to +18V
DRVH to SW............. -0.3V to (BST-SW) + 0.3V
DRVL to VSS...................-0.3V to (VDD + 0.3V)
All Other Pins.....................-0.3V to (VDD + 0.3V)
Thermal Resistance (4)
θJA
θJC
SOIC8E ..................................48...... 10... C/W
QFN8 (3x3mm).......................50...... 12... C/W
QFN9 (3x3mm).......................50...... 12... C/W
QFN10 (4x4mm).....................47....... 7.... C/W
SOIC-8....................................96...... 45... C/W
(2)
Continuous Power Dissipation (TA =25°C)
SOIC8E...................................................... 2.6W
QFN8 (3x3mm) .......................................... 2.5W
QFN9 (3x3mm) .......................................... 2.5W
QFN10 (4x4mm) ...................................... 2.66W
SOIC-8....................................................... 1.3W
Junction Temperature...............................150C
Lead Temperature ....................................260C
Storage Temperature............... -65°C to +150C
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/ θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
MP1921A Rev1.03
12/9/2014
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
3
MPS [ MONOLITHIC POWER SYSTEMS ]
