MP1583 – 3A, 23V, 385KHz STEP-DOWN CONVERTER
To optimize the compensation components for
conditions not listed in Table 2, the following
procedure can be used.
1. Choose the compensation resistor (R3) to set
the desired crossover frequency. Determine R3
by the following equation:
R3
=
2
π ×
C2
×
f
C
V
OUT
×
G
EA
×
G
CS
V
FB
PCB Layout Guide
PCB layout is very important to achieve stable
operation. Please follow these guidelines and
take Figure2 and 3 for references.
1)
Keep the path of switching current short
and minimize the loop area formed by Input
cap, high-side and low-side MOSFETs.
Keep the connection of low-side MOSFET
between SW pin and input power ground
as short and wide as possible.
Ensure all feedback connections are short
and direct. Place the feedback resistors
and compensation components as close to
the chip as possible.
Route SW away from sensitive analog
areas such as FB.
Connect IN, SW, and especially GND
respectively to a large copper area to cool
the chip to improve thermal performance
and long-term reliability. For single layer,
do not solder exposed pad of the IC
R4
R1
R2
2)
Where f
C
is the desired crossover frequency
(which typically has a value no higher than
38KHz).
2. Choose the compensation capacitor (C3) to
achieve the desired phase margin. For
applications with typical inductor values, setting
the compensation zero, f
Z1
, below one forth of
the crossover frequency provides sufficient
phase margin. Determine C3 by the following
equation:
C3
>
4
2
π ×
R3
×
f
C
3)
4)
5)
Where R3 is the compensation resistor value.
3. Determine if the second compensation
capacitor (C6) is required. It is required if the
ESR zero of the output capacitor is located at
less than half of the 385KHz switching
frequency, or if the following relationship is valid:
f
1
<
S
2
π ×
C2
×
R
ESR
2
SS/REF 8
EN 7
6
FB 5
C6
C3
R3
SGND
SGND
COMP
3
SW
If this is the case, then add the second
compensation capacitor (C6) to set the pole f
P3
at the location of the ESR zero. Determine C6
by the equation:
C6
=
C2
×
R
ESR
R3
PGND
4 GND
1 BS
2
IN
Figure 2―PCB Layout (Single Layer)
C4
C5
L1
C1
D1
C2
MP1583 Rev. 3.1
6/20/2011
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9
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