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MP1567DQ-LF 参数 Datasheet PDF下载

MP1567DQ-LF图片预览
型号: MP1567DQ-LF
PDF下载: 下载PDF文件 查看货源
内容描述: [Switching Regulator, Current-mode, 2A, 800kHz Switching Freq-Max, PDSO10, QFN-10]
分类和应用: 开关光电二极管
文件页数/大小: 11 页 / 324 K
品牌: MPS [ MONOLITHIC POWER SYSTEMS ]
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MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER  
PIN FUNCTIONS  
Pin#  
Name Function  
Power Switch Boost. BS powers the gate of the high-side N-Channel power MOSFET switch.  
Connect a 10nF or greater capacitor between BS and SW.  
1
BS  
IN  
Internal Power Input. IN supplies the power to the MP1567 through the internal LDO  
regulator. Bypass IN to PGND with a 10µF or greater capacitor. Connect IN to the input  
source voltage.  
2
3
Output Switching Node. SW is the source of the high-side N-Channel switch and the drain of  
the low-side N-Channel switch. Connect the output LC filter between SW and the output.  
SW  
Power Ground. PGND is the source of the N-Channel MOSFET synchronous rectifier.  
Connect PGND to SGND as close to the MP1567 as possible.  
4
5
PGND  
SGND Signal Ground.  
Soft-Start Input. Place a capacitor from SS to SGND to set the soft-start period. The MP1567  
6
SS  
sources 2µA from SS to the soft-start capacitor at start up. As the voltage at SS rises, the  
feedback threshold voltage increases to limit inrush current at start up.  
Feedback Input. FB is the inverting input of the internal error amplifier. Connect a resistive  
voltage divider from the output voltage to FB to set the output voltage.  
7
8
FB  
COMP  
BP  
Compensation Node. COMP is the output of the error amplifier. Connect a series RC network  
to compensate the regulation control loop.  
Internal 2.4V Regulator Bypass. Connect a 10nF capacitor between BP and SGND to bypass  
the internal regulator. Do not apply any load to BP.  
9
On/Off Control Input. Drive EN high to turn on the MP1567; low to turn it off. For automatic  
startup, connect EN to IN.  
10  
EN  
OPERATION  
The MP1567 measures the output voltage  
through an external resistive voltage divider and  
compares that to the internal 0.9V reference to  
generate the error voltage at COMP. The  
current-mode regulator uses the voltage at  
COMP and compares it to the inductor current  
to regulate the output voltage. The use of  
current-mode regulation improves transient  
response and improves control loop stability.  
inductor current to decrease. The average  
inductor current is controlled by the voltage at  
COMP, which in turn, is controlled by the output  
voltage. Thus the output voltage controls the  
inductor current to satisfy the load.  
Since the high-side N-Channel MOSFET  
requires voltage above VIN to drive its gate, a  
bootstrap capacitor from SW to BS is required  
to drive the high-side MOSFET gate. When SW  
is driven low (through the low-side MOSFET),  
the BS capacitor is internally charged. The  
voltage at BS is applied to the high-side  
MOSFET gate to turn it on, and maintains that  
voltage until the high-side MOSFET is turned  
off and the low-side MOSFET is turned on, and  
the cycle repeats. Connect a 10nF or greater  
capacitor from BS to SW to drive the high-side  
MOSFET gate. Using a larger capacitor does  
little to improve performance.  
At the beginning of each cycle, the high-side  
N-Channel MOSFET is turned on, forcing the  
inductor current to rise. The current at the drain  
of the high-side MOSFET is internally  
measured and converted to a voltage by the  
current sense amplifier. That voltage is  
compared to the error voltage at COMP. When  
the inductor current raises sufficiently, the PWM  
comparator turns off the high-side switch and  
turns on the low-side switch, forcing the  
MP1567 Rev. 2.4  
9/21/2007  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2007 MPS. All Rights Reserved.  
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