MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
Step-Up Converter
Power-On Sequencing and Soft-Start
The MP1531 automatically sequences its
outputs at startup. When EN goes from low to
high, or if EN is held high and the input voltage
VIN rises above the under-voltage lockout
threshold, the outputs turn on in the following
sequence:
The 250KHz fixed-frequency step-up converter
employs a current-mode control architecture
that maximizes loop bandwidth to provide fast-
transient responses needed for TFT LCD
drivers. High switching frequency allows for
smaller inductors and capacitors minimizing
board space and thickness.
1. Step-up converter
Linear Regulators
2. Negative linear regulator (GL)
3. Positive linear regulator (GH)
The positive linear regulator (GH) uses a
P-Channel pass element to drop the input
voltage down to the regulated output voltage.
The feedback of the positive linear regulator is
Each output turns on with a soft-start voltage
ramp. The soft-start ramp period is set by the
timing capacitor connected between CT and
GND. A 10nF capacitor at CT sets the soft-start
ramp period to 6ms. The timing diagram is
shown in Figure 2.
a
conventional error amplifier with the
regulation threshold at 1.25V.
The negative linear regulator (GL) uses a
N-Channel pass element to raise the negative
input voltage up to the regulated output voltage.
The feedback threshold for the negative linear
regulator is ground. The resistor string goes
from REF (1.25V) to FB2 and from FB2 to GL to
set the negative output voltage, VGL.
After the MP1531 is enabled, the power-on
reset spans three periods of the CT ramp. First
the step-up converter is powered up with
reference to the CT ramp and allowed one
period of the CT ramp to settle. Next the
negative linear regulator (GL) is soft-started by
ramping REF, which coincides with the CT
ramp, and also allowed one CT ramp period to
settle.
The difference between the voltage at IN3 and
the voltage at IN2 is limited to 60V abs. max.
Fault Sensing and Timer
Each of the 3 outputs has an internal
comparator that monitors its respective output
voltage by measuring the voltage at its
respective FB input. When any FB input
indicates that the output voltage is below
approximately 80% of the correct regulation
The positive linear regulator (GH) is then
soft-started and allowed to settle in one period
of CT ramp. Nine periods of the CT ramp have
occurred since the chip enabled. If all outputs
are in regulation (>80%), the CT will stop
ramping and be held at ground. The RDY pin
will be pulled down to an active low. If any FB
voltage remains below regulation (<80%) after
voltage, the fault timer enables and the RDY
pin goes high impedance. The fault timer uses
the same CT capacitor as the soft-start
sequencer. If any fault persists to the end of the
fault timer (One CT cycle is 6ms for a 10nF
capacitor), all outputs are disabled. Once the
outputs are shut down due to the fault timer, the
MP1531 must be re-enabled by either cycling
EN or by cycling the input power. When re-
enabled, the MP1531 cycles through the normal
power-on sequence. If the fault persists for less
the nine CT periods, RDY will remain high and
CT will begin its fault timer pulse.
than the fault timer period, RDY will be pulled
low and the part will function as though no fault
has occurred.
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
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