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MP1496SGJ 参数 Datasheet PDF下载

MP1496SGJ图片预览
型号: MP1496SGJ
PDF下载: 下载PDF文件 查看货源
内容描述: [High-Efficiency, 2A, 16V, 500kHz Synchronous, Step-Down Converter]
分类和应用:
文件页数/大小: 15 页 / 584 K
品牌: MPS [ MONOLITHIC POWER SYSTEMS ]
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MP1496S – SYNCHRONOUS, STEP-DOWN CONVERTER WITH INTERNAL MOSFETS  
Over-Current Protection and Hiccup  
The MP1496S has a cycle-by-cycle over-current  
limit when the inductor current peak exceeds the  
set current-limit threshold. Meanwhile, output  
voltage drops until FB falls below the under-  
voltage (UV) threshold—typically 50% below the  
reference. Once UV triggers, the MP1496S  
enters hiccup mode to periodically restart the  
part. This protection mode is especially useful  
when the output is dead-shorted to ground. This  
greatly reduces the average short circuit current,  
alleviates thermal issues, and protects the  
regulator. The MP1496S exits hiccup mode once  
the over current condition is removed.  
Figure 3: Internal Bootstrap Startup and Shutdown  
Charging Circuit  
If both VIN and EN exceed their appropriate  
thresholds, the chip starts. The reference block  
starts first, generating stable reference voltages  
and currents, and then the internal regulator is  
enabled. The regulator provides stable supply for  
the remaining circuitries.  
LS-FET Negative Current Limit Protection  
To prevent LS-FET current goes too negative,  
The MP1496S will sense the LS-FET  
current during LS-FET turn on period. It provides  
cycle-by-cycle negative current limit protection  
when the inductor valley current is lower than the  
set negative current limit. Internal 500kHz or  
250kHz (fold-back frequency) clock initiates the  
PWM cycle, If LS-FET negative current limit is  
triggered before internal clock comes, LS-FET  
will turn off and wait for internal clock to turn on  
HS-FET. In this case, MP1496S will work at DCM  
mode. If LS-FET negative current limit is not  
triggered in a clock cycle, MP1496S works at  
CCM mode. During soft start period, the LS-FET  
negative current limit is gradually decrease from  
0A(typical) to -1A (typical).  
Three events can shut down the chip: EN low, VIN  
low, and thermal shutdown. In shutdown, the  
signaling path is first blocked to avoid any fault  
triggering. The COMP voltage and the internal  
supply rail are then pulled down. The floating  
driver is not subject to this shutdown command.  
Thermal Shutdown  
Thermal shutdown prevents the chip from  
operating at exceedingly high temperatures.  
When the silicon die temperature exceeds  
150°C, the whole chip shuts down. When the  
temperature drops below its lower threshold—  
typically 130°C—the chip is enabled again.  
Floating Driver and Bootstrap Charging  
An external bootstrap capacitor powers the  
floating power MOSFET driver. This floating  
driver has its own UVLO protection with a rising  
threshold of 2.2V and a hysteresis of 150mV.  
The bootstrap capacitor voltage is regulated  
internally by VIN through D1, M1, C4, L1 and C2  
(see Figure 3). If (VIN-VSW) exceeds 5V, U1 will  
regulate M1 to maintain a 5V BST voltage across  
C4. A 10resistor placed between SW and BST  
cap is strongly recommended to reduce SW  
spike voltage.  
MP1496S Rev.1.1  
3/29/2017  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2017 MPS. All Rights Reserved.  
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