MP1048 – FULL BRIDGE CCFL CONTROLLER
PIN FUNCTIONS
Pin #
Name
Description
1
SI
Secondary Current Feedback Input. Connect a current sense resistor from the cold end of the
secondary winding to ground. Connect this pin to the junction of the resistor and the secondary
winding. If the voltage at SI exceeds +1.2V, a pulse of current will pull down on the COMP pin in
an attempt to regulate the secondary current and the Fault Timer will be started.
2
3
LI
Lamp Current Feedback Input. Connect this pin to the cold end of the lamp and shunt a sense
resistor to ground. The sense amplifier will sink a current from the COMP pin that is proportional
to the absolute value of the voltage at this pin. (In regulation the average of the absolute value of
the voltage at this pin is determined by the voltage at the ABRT pin).
LV
Lamp Voltage Feedback Input. Connect a capacitive voltage divider from the hot end of the lamp
to ground. Connect this pin to the tap on the divider and shunt a bias resistor to ground. If the
voltage at LV exceeds +1.2V, a pulse of current will pull down on the COMP pin to attempt to
regulate the lamp voltage and the Fault Timer will be started.
4
5
6
7
COMP Feedback Compensation Node. Connect a compensation capacitor from this pin to ground.
AG
FT
Analog Ground.
Fault Timing. Connect a timing capacitor from this pin to AG to set the fault timeout period.
LCS
Lamp Operating Clock Set. Connect a resistor from this pin to AG. This resistor sets the
operating frequency of the MP1048.
8
LCC
Lamp Clock Control. LCC provides compensation when the operating clock is swept in order to
strike the lamp. Connect a resistor in series with a capacitor from LCC to AG. Connect a smaller
capacitor directly from LCC to AG. Connect only a single capacitor to AG, if some sweeping of
the operating clock can be tolerated during open lamp conditions. Connect LCC to AG to force
the operating clock to the selected value at all times.
9
BRC
BRS
Burst Repetition Rate Control. Connect BRC to AG.
10
Burst Repetition Rate Setting. If the burst repetition rate is to be synchronized to an external
clock, connect a capacitor from BRS to AG. If the burst rate generator is free-run and will not be
synchronized with an external clock, connect a resistor in parallel with a capacitor from BRS to
AG. If the burst is to be controlled by an external logic signal, connect BRS to VCC and apply the
logic signal to the DBRT pin.
11
12
DBRT
ABRT
Burst-Mode (Digital) Brightness Control Input. The voltage range of 0V to 1.2V at DBRT linearly
sets the burst-mode duty cycle from minimum 10% to 100%. If burst dimming is not used, tie
DBRT to VCC.
Analog Brightness Control Input. The voltage range of 0V to 1.2V at ABRT sets the 3:1 dimming
range for the lamp current. If analog dimming is not used, tie ABRT to VCC.
13
14
15
EN
NC
Enable Input. Pull EN high to turn on the MP1048; low to turn it off.
No Connect.
PRR
Input Power Rail, Right-Side. Connect PRR directly to the drain of the high-side, right-side,
external power MOSFET.
16
17
18
19
BTR
UGR
Output Bootstrap, Right-Side. BTR provides gate bias for the right-side high-side MOSFET.
Connect a capacitor from BTR to OUTR.
High-Side MOSFET Gate Output, Right-Side. Connect UGR to the gate of the high-side,
right-side, external power MOSFET.
OUTR
VCCR
Bridge Output, Right-Side. Connect OUTR to the source of the right-side, high-side
MOSFET and the drain of the low-side, right-side MOSFET.
Voltage Rail Output, Right-Side. VCCR allows bypassing the bias supply for the control
circuitry. Bypass VCCR with a 0.47µF capacitor. Connect to VCCL.
MP1048 Rev. 0.9
9/24/2007
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4
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