MPQ2451-5/33―36V, 2.2MHz, 0.6A, STEP-DOWN CONVERTER, AEC-Q100 QUALIFIED
OPERATION
The MPQ2451-5/33 is a 2.2MHz, asynchronous,
step-down, switching regulator with an integrated
high-side, high-voltage, power MOSFET. It
provides an internally-compensated, highly-
efficient output of up to 0.6A with current-mode
control. It also features a wide input voltage
range, internal soft-start control, and a precise
current limit. Its very-low, operational, quiescent
current makes it suitable for battery-powered
applications.
drives the COMP output high, driving the switch
peak current to rise and deliver more energy to
the output. Conversely, when VFB rises above
VREF, the switch peak current output drops.
Internal Regulator
The 2.6V internal regulator powers most of the
internal circuitry. This regulator takes the VIN
input and operates in the full VIN range. When VIN
exceeds 3.0V, the output of the regulator is in full
regulation. When VIN drops below 3.0V, the
output degrades.
PWM Control
At moderate-to-high output current, the
MPQ2451-5/33 operates in a fixed-frequency,
peak-current-control mode to regulate the output
voltage. A PWM cycle—initiated by the internal
clock—turns the power MOSFET on, and the
MOSFET remains on until its current reaches the
value set by VCOMP. When the PWM signal goes
low, the power switch turns off and remains off
for at least 100ns before the next cycle starts.
Enable Control
The MPQ2451-5/33 has a dedicated enable
control pin, EN. When VIN rises above threshold,
the EN pin can enable or disable the chip for
HIGH effective logic. Its falling threshold is 1.2V,
and its rising threshold is about 1.6V. When left
floating, the EN pin is internally pulled down to
GND to disable the chip.
When the EN voltage is pulled to 0V, the chip
enters the lowest shutdown current mode.
Between 0V and the rising threshold, the chip
remains in shutdown mode with a slightly higher
shutdown current.
If the current in the power MOSFET does not
reach the COMP-set current value within one
PWM cycle, the power MOSFET remains ON to
avoid a turn-off operation.
Pulse-Skipping Mode
Under-Voltage Lockout (UVLO)
Under light-load conditions, the MPQ2451-5/33
enters pulse-skipping mode to improve efficiency.
Pulse-skipping occurs when VCOMP drops below
the internal sleep threshold, which generates a
PAUSE command to block the turn-on clock
pulse so the power MOSFET does not turn ON;
this procedure reduces gate driving and
switching losses. This PAUSE command causes
the whole chip to enter sleep mode, reducing the
quiescent current to further improve light-load
efficiency.
VIN under-voltage lockout (UVLO) protects the
chip from operating at an insufficient supply
voltage. The UVLO rising threshold is ~2.9V
while its falling threshold is 2.6V.
Internal Soft-Start
A reference-type soft-start (SS) prevents the
converter-output voltage from overshooting
during startup. When the chip starts, the internal
circuitry generates a soft-start voltage (VSS) that
ramps up from 0V over the SS time. When VSS is
less than VREF, VSS overrides VREF as the error
amplifier reference.
When VCOMP exceeds the sleep threshold, the
PAUSE signal resets and the chip resumes
normal PWM operation. Whenever the PAUSE
changes state from LOW to HIGH, the PWM
signal immediately goes HIGH and turns on the
power MOSFET.
The maximum VSS is approximately the same as
VFB; i.e. if VFB falls, the maximum of VSS falls. This
accommodates short-circuit recovery; when the
short-circuit is removed, VSS ramps up to prevent
output-voltage overshoot.
Error Amplifier
The error amplifier is composed of an internal op-
amp with an RC feedback network connected
between its output node (COMP) and its negative
input node (FB). When VFB drops below the
internal reference voltage (VREF), the op-amp
MPQ2451-5/33 Rev 1.0
5/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
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