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HR1001LGS 参数 Datasheet PDF下载

HR1001LGS图片预览
型号: HR1001LGS
PDF下载: 下载PDF文件 查看货源
内容描述: [Enhanced LLC Controller with Adaptive Dead-Time Control]
分类和应用:
文件页数/大小: 25 页 / 1626 K
品牌: MPS [ MONOLITHIC POWER SYSTEMS ]
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HR1001L ENHANCED LLC CONTROLLER  
PIN FUNCTIONS (continued)  
Pin #  
Name Description  
Input voltage sense and brown-in/brown-out protection. If the voltage on BO is over  
2.3V, the IC enables the gate driver. If the voltage on BO is below 1.81V, the IC is disabled.  
7
BO  
IC latch off. When the voltage on LATCH exceeds 1.85V, the IC shuts down and lowers its  
bias current to its pre-start-up level. LATCH is reset when the voltage on VCC is  
discharged below its UVLO threshold. Connect LATCH to GND if the function is not used.  
Half-bridge dV/dt sense. To detect the dV/dt of the half-bridge, a high-voltage capacitor is  
connected between SW and HBVS. The dV/dt current through HVBS is used to adjust the  
dead-time adaptively between the high-side gate and the low-side gate.  
Ground. GND is the current return for both the low-side gate driver and the IC bias.  
Connect all external ground connections with a trace to GND, one for signals and a second  
for pulsed current return.  
8
9
LATCH  
HBVS  
GND  
10  
Low-side gate driver output. The driver is capable of a 0.8A of source/sink peak current  
to drive the lower MOSFET of the half-bridge. LG is pulled to GND during UVLO.  
Supply voltage. VCC supplies both the IC bias and the low-side gate driver. Use a small  
bypass capacitor (e.g.: 0.1µF) to get a clean bias voltage for the IC signal.  
High-voltage spacer. No internal connection. NC isolates the high-voltage pin and eases  
compliance with safety regulations (creepage distance) on the PCB.  
High-side switch source. SW is the current return for the high-side gate drive current. SW  
requires careful layout to prevent large spikes below ground.  
11  
12  
13  
14  
LG  
VCC  
NC  
SW  
High-side floating gate driver output. HG is capable of a 0.8A source/sink peak current  
to drive the upper MOSFET of the half-bridge. Connect an internal resistor to SW to ensure  
that HG does not float during UVLO.  
Bias for floating voltage supply of the high-side gate driver. Connect a bootstrap  
capacitor between BST and SW. This capacitor is charged by an internal bootstrap diode  
driven in phase with the low-side gate driver.  
15  
16  
HG  
BST  
HR1001L Rev.1.0  
4/18/2016  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2016 MPS. All Rights Reserved.  
11