HR1000 – RESONANT HALF-BRIDGE CONTROLLER
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION – INTERNAL USE ONLY
PIN FUNCTIONS (continued)
Pin #
Name Description
Input Voltage Sense. Connect to the high-voltage input bus through the tap of a resistor
divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage
below 1.25V shuts down (without latching) the IC, lowers its consumption and discharges
the soft-start capacitor. The IC operation resumes (with soft-start) when the voltage
exceeds 1.25V. The comparator has current hysteresis: An internal 12µA current source is
ON as long as the applied voltage is below 1.25V, and is OFF if this value is exceeded.
Bypass the pin with a capacitor to GND to reduce noise pick-up. An internal Zener diode
top-limits the pin voltage. Activating the Zener diode causes the IC to shut down (without
latching). Bias the pin between 1.25V and 5.5V if the function is not used.
7
BO
IC Latch. Connects internally to a comparator that—when the pin voltage exceeds 1.85V—
shuts the IC down and brings its consumption to near pre-start-up levels. The latch is
removed as the VCC voltage goes below the UVLO threshold. Tie the pin to GND if the
function is not used.
8
9
LATCH
PFC
Interface to the front-end PFC. This pin—normally high—stops the PFC controller for
protection purposes or during burst-mode operation. It goes low when the IC shuts down
from the following conditions: VCC > 16V, LATCH > 1.85V, CS > 1.5V, BO > 5.5V, thermal
shutdown and BURST < 1.25V. The pin also goes low when the voltage on TIMER
exceeds 2V, and goes back open as the voltage falls below 0.3V. During UVLO, it is open.
Leave the pin unconnected if not used.
Ground. Current return for both the low-side gate-driver current and the IC bias current. Tie
all bias component ground connections to a trace to this pin. Keep separate from any
pulsed current return.
10
11
GND
LG
Low-Side Gate Driver. The driver is capable of a minimum 0.5A source and a minimum 1A
sink-peak current to drive the lower MOSFET of the half-bridge leg. The pin is actively
pulled to GND during UVLO.
Supply Voltage. Supplies both the IC signal and the low-side gate driver. Sometimes a
small bypass capacitor (e.g., 0.1µF) can help provide a clean bias voltage for the IC signal.
12
13
14
VCC
N.C.
SW
High-Voltage Spacer. Not internally connected—isolates the high-voltage pin and eases
compliance with safety regulations (creepage-distance) on the PCB.
High-Side Switch Source. Current return for the high-side gate-drive current. Requires
careful layout to avoid large spikes below ground.
High-Side Floating Gate-Driver. Capable of minimum 0.5A source and minimum 1A sink-
peak current to drive the upper MOSFET of the half-bridge leg. An internal resistor
connected to pin 14 (SW) ensures that the pin does not floating during UVLO.
15
16
HG
High-Side Gate Driver for Floating Voltage Supply. Connect a bootstrap capacitor between
this pin and pin 14 (SW)—fed by an internal bootstrap diode driven in-phase with the low-
side gate-drive.
BST
HR1000 Rev. 1.04
10/11/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
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