HR1000A – RESONANT HALF-BRIDGE CONTROLLER
Figure 5: Bust-mode Operation Set-up for Wide
Input Voltage Range
Figure 6: PFC Disable Block Diagram
The HR1000A provide PFC disabling. Pull the
PFC pin low for one of following conditions:
RB1 and RB2 from Figure 5 correct against the
wide input voltage range. Select both resistors
based on experimental results. Note that the
total resistance of RB1 and RB2 should be much
bigger than RH to minimize the effect on the BO
pin voltage.
•
gate-off
(Burst<1.25V);
during
burst-mode
•
OCP (CS>1.5V); input over-voltage
(BO>5.5V);
During burst-mode operation, when the load is
lower than PBurst, the switching frequency is
clamped at the maximum frequency. Then the
output voltage must rise over the set value,
which would increase the current flowing
•
•
Latch pin HIGH (Latch>1.85V);
TIMER pin voltage exceeding 2V
without dropping to 0.3V; and
•
over-temperature protection triggering.
through the
opto-coupler. Therefore, the
voltage on Rfmax must rise due to the increased
opto-transistor current. The Burst pin voltage
would then drop below 1.25V, triggering the
gate signal OFF state. Until the output voltage
falls below the setting value, the current flow
through opto-coupler then decreases, causing
the Burst pin voltage to rise. When the voltage
exceeds 1.25V+100mV, the IC restarts to
generate the gate signal. The IC will continue to
operate in this mode under no-load or light-load
to decrease average power consumption.
Shutdown the PFC to reduce power
consumption or to protect the system. Figure 7
shows the typical application circuit between
the HR1000A and the PFC controller
(MP44010/1 is a PFC Controller).
PFC-Disable Function
Many applications require a PFC function,
making a pre-regulator widely before a resonant
circuit common. Under some conditions—e.g.
no-load or light load, OCP, OVP—require
disabling the PFC.
Figure 7: Communication Circuit between
HR1000A and PFC Controller
If this function is not used, PFC pin can float.
HR1000A Rev. 1.01
8/30/2012
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