HFC0100—QUASI RESONANT CONTROLLER
Burst Operation
Current Limit Setting
To minimize the power dissipation in no load or
light load, the HFC0100 enters the burst mode
operation. As the load decreases, the FB voltage
decreases,, the HFC0100 stops the switching
cycle when the FB voltage drops below the
threshold VBURL—0.5V. And the output voltage
starts to drop at a rate dependent on the load.
This causes the FB voltage to rise again. Once
The switch current is sensed by the resistor
series between the Source of the FET and the
ground. And the current limit is determined by the
VFB VFB
FB signal, VLimit
=
=
. To limit the
Idiv
3
maximum output power, the current limit is
clamped at 1V when VFB is bigger than 3.3V.
Leading Edge Blanking
the FB voltage exceeds the threshold VBURH
—
0.7V, switching resumes. The FB voltage then
falls and rises repeatedly. The burst mode
operation alternately enables and disables
switching cycle of the MOSFET thereby reducing
switching loss in the no load or light load
conditions.
In order to avoid the premature termination of the
switching pulse due to the parasitic capacitance,
an internal leading edge blanking (LEB) unit is
employed between the CS Pin and the current
comparator input. During the blanking time, the
path, CS Pin to the current comparator input, is
blocked. Figure 9 shows the leading edge
blanking.
Figure 8 shows the typical FB and Drive
waveform during the burst mode.
VBURH:0.7V
VLimit
VBURL:0.5V
TLEB=250nS
V
FB
200mV/div
V
Drive
5V/div
40us/div
t
Figure 8—Burst Mode
Thermal Shutdown (TSD)
To prevents from any lethal thermal damage. The
HFC0100 shuts down switching cycle when the
inner temperature exceeds 150DegC. As soon as
the inner temperature drops below 100DegC, the
power supply resumes operation.
Figure 9—Leading Edge Blanking
Over Power Compensation
In the case of current sensing, shows as figure
10, the turn off of the FET is delayed due to the
propagation delay of the control circuit, the delay
time is the inherent characteristic of the control
circuit, so Tdelay can be seen fixed. This delay will
cause an overshoot of the peak current. △I2 is
bigger than △I1 due to the bigger rising ratio(the
higher input voltage, the bigger rising ratio).
Soft-Start
To reduce the stress on primary MOSFET and
secondary diode during start up, to smoothly
establish the output voltage, the HFC0100 has
an internal soft-start circuit that increases the
current comparator inverting input voltage,
together with the MOSFET current, slowly after it
starts up. The pulse width to the power switching
device is progressively increased to establish the
correct working conditions for transformers,
inductors, and capacitors.
HFC0100 Rev. 1.01
9/23/2011
www.MonolithicPower.com
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© 2011 MPS. All Rights Reserved.
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