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HFC0100HS-Z 参数 Datasheet PDF下载

HFC0100HS-Z图片预览
型号: HFC0100HS-Z
PDF下载: 下载PDF文件 查看货源
内容描述: [Switching Controller, Current-mode, 100kHz Switching Freq-Max, PDSO8, SOIC-8]
分类和应用: 开关光电二极管
文件页数/大小: 15 页 / 285 K
品牌: MPS [ MONOLITHIC POWER SYSTEMS ]
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HFC0100QUASI RESONANT CONTROLLER  
OPERATION  
The HFC0100 incorporates all the necessary  
features needed to a reliable Switch Mode Power  
Supply. Its valley detector ensures minimum  
Drain-Source voltage switching (Quasi-Resonant  
operation). When the output power falls below a  
given level, the regulator enters the burst mode.  
An internal minimum off time limiter prevents the  
free running frequency to exceed 150kHz.  
Start-Up  
Figure 2—Valley Detector  
Initially, the IC is self supplying from the internal  
high voltage current source unit which drawn  
from the HV pin.  
The IC starts switching and the internal high  
voltage current source unit is stopped as soon as  
the voltage on Pin Vcc reaches the threshold  
VCCH—11.8V.  
Before the supply is taken over by the auxiliary  
winding of the transformer, the Vcc capacitor  
supplies HFC0100 to maintain Vcc.  
V
DS  
100V/div  
Valley Switching  
Quasi-Resonant Operation  
4us/div  
The HFC0100 operates in Discontinuous  
Conduction Mode (DCM). The valley detector  
Figure 3—Valley Switching  
ensures  
minimum  
Drain-Source  
voltage  
To ensure the switching frequency below the  
EN55022 start limit---150kHz, HFC0100 employs  
an internal minimum off time limiter---7.8μS,  
shows as figure 4.  
switching (Quasi-Resonant operation)  
As a result, there are virtually no primary switch  
turn on losses and no secondary diode recovery  
losses. It ensures the reduction of the EMI noise.  
Figure2 shows the valley detector unit.  
When the voltage:  
Naux  
24kΩ  
(VDS V )x  
x
< 55mV  
in  
Npri 24kΩ + RVSD  
VDS —Drain Source Voltage of the primary FET  
VIN—Input Voltage  
V
DS  
100V/div  
Toff7.8uS  
Naux —Auxiliary Winding Turns of the transformer  
Npri —Primary Winding Turns of the transformer  
2us/div  
Figure 4—Minimum Off Time Limit  
The valley detector sends out a valley signal to  
turn on the primary FET.  
Figure3 shows a typical drain source voltage  
waveform with valley switching.  
HFC0100 Rev. 1.01  
9/23/2011  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2011 MPS. All Rights Reserved.  
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