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XPC860PCZP50D3 参数 Datasheet PDF下载

XPC860PCZP50D3图片预览
型号: XPC860PCZP50D3
PDF下载: 下载PDF文件 查看货源
内容描述: 系列硬件规格 [Family Hardware Specifications]
分类和应用:
文件页数/大小: 76 页 / 805 K
品牌: MOTOROLA [ MOTOROLA ]
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Features  
MPC8xx core that incorporates memory management units (MMUs) and instruction and  
data caches and that implements the PowePC instruction set. The communications  
processor module (CPM) from the MC68360 QUICC has been enhanced by the addition of  
the inter-integrated controller (I2C) channel. The memory controller has been enhanced,  
enabling the MPC860 to support any type of memory, including high-performance  
memories and new types of DRAMs. A PCMCIA socket controller supports up to two  
sockets. A real-time clock has also been integrated.  
Table 1 shows the functionality supported by the members of the MPC860 family.  
Table 1. MPC860 Family Functionality  
Cache (Kbytes)  
Ethernet  
1
Part  
ATM  
SCC  
Ref.  
Instruction  
Cache  
Data Cache  
10T  
10/100  
MPC860DE  
MPC860DT  
MPC860DP  
MPC860EN  
MPC860SR  
MPC860T  
4
4
4
4
8
4
4
4
8
4
Up to 2  
Up to 2  
Up to 2  
Up to 4  
Up to 4  
Up to 4  
Up to 4  
1
1
2
2
2
4
4
4
4
1
1
yes  
yes  
1,2,3  
1,2,3  
1
16  
4
1
1
4
yes  
yes  
yes  
yes  
1,2  
4
1,2,3  
1,2,3  
4
MPC860P  
MPC855T  
16  
4
1
1
1
Supporting documentation for these devices refers to the following:  
1. MPC860 PowerQUICC User’s Manual (MPC860UM/D, Rev. 1).  
2. MPC8XX ATM Supplement (MPC860SARUM/AD).  
3. MPC860T (Rev. D), Fast Ethernet Controller Supplement (MPC860TREVDSUPP).  
4. MPC855T User’s Manual (MPC855TUM/D, Rev. 1).  
Part II Features  
The following list summarizes the key MPC860 features:  
• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC  
architecture) with thirty-two 32-bit general-purpose registers (GPRs)  
— The core performs branch prediction with conditional prefetch, without  
conditional execution  
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)  
– 16-Kbyte instruction caches are four-way, set-associative with 256 sets;  
4-Kbyte instruction caches are two-way, set-associative with 128 sets.  
– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data  
caches are two-way, set-associative with 128 sets.  
– Cache coherency for both instruction and data caches is maintained on 128-bit  
(4-word) cache blocks.  
2
MPC860 Family Hardware Specifications  
MOTOROLA